STA020DJ STMicroelectronics, STA020DJ Datasheet
STA020DJ
Specifications of STA020DJ
Available stocks
Related parts for STA020DJ
STA020DJ Summary of contents
Page 1
DIGITAL AUDIO INTERFACE TRANSMITTER MONOLITHIC DIGITAL AUDIO INTERFACE TRANSMITTER 3.3V SUPPLY VOLTAGE SUPPORTS: – AES/EBU, IEC 958, – S/PDIF, & EIAJ CP-340 – Professional and Consumer Formats PARITY BITS AND CRC CODES GENERATED TRANSPARENT MODE ALLOWS DIRECT CONNECTION OF ...
Page 2
STA020 ABSOLUTE MAXIMUM RATINGS Symbol V DC Power Supply D+ V Digital Input Voltage IND T Ambient Operating Temperature (power applied) amb T Storage Temperature stg RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground) Symbol Parameter ...
Page 3
PIN DESCRIPTION (continued) N° Pin 7 FSYNC Frame Sync. Delineates the serial data and may indicate the particular channel, left or right and may be an input or output. The format is based on M0, M1 and M2 pins. 8 ...
Page 4
STA020 PIN DESCRIPTION (continued) N° Pin 24 TRNPT/FC1 Transparent Mode/Frequency Control 1. In professional mode, setting TRNPT low selects normal operation & CBL is an output. Setting TRNPT high, allows the STA020D to be connected directly to an STA120. In ...
Page 5
Figure 2. STA020D Typical Connection Diagram. AUDIO DATA PROCESSOR DECODER SUBCODE PORT RESET CONTROL CHANNEL STATUS BITS CONTROL GENERAL DESCRIPTION The STA020D is a monolithic CMOS circuit that encodes and transmits audio and digital data according to the AES/EBU, IEC ...
Page 6
STA020 formation from it, and transmit it as user data. The master clock , MCK, controls timing for the entire chip and must be 128xFs example, if stereo data is input to the STA020D at 44.1kHz, MCK input ...
Page 7
Figure 3. Audio Serial Port Formats. FORMAT 0: FSYNC(out) SCK(out) SDATA(in) FORMAT 1: FSYNC(in) SCK(in) SDATA(in) FORMAT 2: FSYNC(in) SCK(in) SDATA(in) FORMAT 3: (RESERVED) FORMAT 4: FSYNC(in) SCK(in) SDATA(in) FORMAT 5: FSYNC(in) SCK(in) SDATA(in) FORMAT 6: FSYNC(in) SCK(in) SDATA(in) FORMAT ...
Page 8
STA020 RST and CBL (TRNPT is low) When RST goes low, the differential line drivers are set to ground. In order to properly synchronize the ST020 to the audio serial port, the transmit timing counters, which include CBL, are not ...
Page 9
Transparent Mode In certain applications it is desirable to receive digital audio data with the STA120 and retransmit it with the STA020D. In this case, channel status, user and validity information must pass through unaltered. For studio environments, AES recommends ...
Page 10
STA020 Table 3. Sample Frequency Encoding FC1 FC0 Figure 5. Transparent Mode Interface. Figure 6. Block Diagram - Professional Mode SDATA SERIAL 6 SCK PORT 7 LOGIC FSYNC ...
Page 11
Figure 7. Block Diagram - Consumer Mode SDATA SERIAL 6 SCK PORT 7 LOGIC FSYNC REGISTERS 9 V MUX PRO FC0 FC1 C2 C3 +3. ...
Page 12
STA020 mm DIM. MIN. TYP. MAX. A 2.35 2.65 0.093 A1 0.10 0.30 0.004 B 0.33 0.51 0.013 C 0.23 0.32 0.009 (1) 15.20 15.60 0.598 D E 7.40 7.60 0.291 e 1.27 H 10.0 10.65 0.394 h 0.25 0.75 ...
Page 13
REVISION HISTORY Date Revision 14-Oct-2002 5 Technical Migration from ST-PRESS to EDOCS 26-Apr-2010 6 Major revision for revalidation process Changes STA020 13/14 ...
Page 14
... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...