LM97593VH National Semiconductor, LM97593VH Datasheet
LM97593VH
Specifications of LM97593VH
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LM97593VH Summary of contents
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... Diversity Receiver Chipset. Block Diagram 1 FIGURE 1. Diversity Receiver Chipset Block Diagram © 2008 National Semiconductor Corporation Features ■ 100% Software compatible with the CLC5903 ■ Pin compatible with the CLC5903 except for the analog input and reference section ■ ...
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... Connection Diagram Ordering Information Industrial (−40°C to +85°C) Block Diagram 2 www.national.com FIGURE 2. LM97593VH PQFP Pinout LM97593VH 128 Pin PQFP LM97593EB Evaluation Board FIGURE 3. LM97593 Block Diagram 2 30008702 Package 30008703 ...
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Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit ANALOG I/O V A− Analog Input 27 V B− Analog Input Control / Analog Input REF V ...
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Pin No. Symbol Equivalent Circuit 99 SCK_IN Input 81 SFS Output 84, 86:88, 90, 91, 93:97, POUT[15:0] Output 104:106, 108, 109 112:114 POUT_SEL[2:0] Input 111 POUT_EN Input 77 RDY Output 37 CK Input 46 SI Input 62, 63, 69:73, D[7:0] ...
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Pin No. Symbol Equivalent Circuit 58 WR Input 60 CE Input 116 TDO Output 117 TDI Input 118 TMS Input 119 TCK Input 121 TRST Input 122 SCAN_EN Input Digital Power Supplies 38, 39, 64, V 79, 92, 102, DDC ...
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... Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ADC Analog, Digital and IO Supply Voltages ( and Difference between and Positive Core Supply Voltage (V ) D18 Voltage on Any Input or Output Pin (Not to exceed 4 ...
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Symbol Parameter SINAD Signal-to-Noise and Distortion Effective Number of Bits ENOB (Relative to Full Scale) THD Total Harmonic Distortion H2 Second Harmonic Distortion H3 Third Harmonic Distortion SFDR Spurious Free Dynamic Range IMD Intermodulation Distortion Dynamic Gain Error INTERCHANNEL CHARACTERISTICS ...
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Symbol Parameter SNR Signal-to-Noise Ratio SINAD Signal-to-Noise and Distortion SFDR Spurious Free Dynamic Range DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V +1.8V, Internal ...
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AC Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, V (±10%), V = +1.8V (±10%), Internal V D18 48, F2 Decimation = 2. Typical values are for ...
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Symbol t TCK Pulse Width Low (Figure 14) JCL JTAG TCK Maximum Frequency (Figure 14) FMAX Microprocessor Interface t Control Setup before the controlling signal goes low (Figure 15) CSU t Control hold after the controlling signal goes high (Figure ...
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DDC Timing Diagrams FIGURE 5. LM97593 Synchronization Input (SI) Timing FIGURE 4. LM97593 Master Reset Timing FIGURE 6. LM97593 Clock Timing FIGURE 7. LM97593 DVGA Interface Timing FIGURE 8. LM97593 Dual Chip Mode Timing 11 30008705 30008706 30008707 30008708 30008709 ...
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FIGURE 11. LM97593 Parallel Output Data Ready Timing www.national.com FIGURE 9. LM97593 Parallel Output Enable Timing FIGURE 10. LM97593 Parallel Output Select Timing FIGURE 12. LM97593 Debug Mode Timing 12 30008710 30008711 30008712 30008713 ...
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FIGURE 13. LM97593 Serial Port Timing FIGURE 14. LM97593 JTAG Port Timing 13 30008714 30008715 www.national.com ...
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FIGURE 15. LM97593 Control I/O Timing 14 30008716 ...
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ADC Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, V +3.3V +1.8V 0V, Internal V D18 Stabilizer On. Boldface limits apply for ...
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ADC Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, V +3.3V +1.8V 0V, Internal V D18 Stabilizer On. Boldface limits apply for T SNR, ...
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SNR, SINAD, SFDR vs 52MSPS -9dBFS) CLK IN 300087110 SNR, SINAD, SFDR vs 52MSPS -3dBFS) CLK IN 300087112 SNR, SINAD, SFDR vs 65MSPS, A ...
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Distortion vs 65MSPS, A CLK Spectral Response @ 20MHz Input (f = 52MSPS, A CLK Spectral Response @ 20MHz Input (f = 65MSPS, A CLK www.national.com IN = -3dBFS) IN 300087116 = -9dBFS) IN 300087118 = -9dBFS) ...
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Spectral Response @ 250MHz Input (f = 52MSPS -9dBFS) CLK IN 300087122 Spectral Response @ 250MHz Input (f = 65MSPS -9dBFS) CLK IN 300087124 IMD 246MHz 250MHz 1IN 2IN (f = 65MSPS, ...
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CIC Output Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, V +3.3V +1.8V 0V, Internal V D18 Stabilizer On. Boldface limits apply for T ...
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Spectral Response @ 250MHz Input (f = 65MSPS -9dBFS) CLK IN 300087132 Spectral Response @ 250MHz Input (f = 65MSPS -3dBFS) CLK IN 21 300087133 www.national.com ...
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DDC Output Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = D18GND = DRGND = 0V, V +3.3V +1.8V 0V, CIC decimation = 8, Internal V D18 pF/pin, Duty Cycle ...
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Spectral Response @ 250MHz Input (f = 65MSPS -9dBFS) CLK IN 300087140 Spectral Response @ 250MHz Input (f = 65MSPS -3dBFS) CLK IN 23 300087141 www.national.com ...
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Functional Description FIGURE 16. LM97593 Dual ADC / Digital Tuner / AGC Block Diagram with Control Register Associations The LM97593 contains two identical 12-bit ADCs driving the digital down-conversion (DDC) circuitry shown in the block diagram in Figure 16. ADC ...
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Page select bits allow access to the overlaid A and B set of FIR coefficients. JTAG boundary scan and on-chip diagnostic circuits are pro- vided to simplify system debug and test. The LM97593 supports 3.3V I/O even though ...
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180 degrees out of phase with REF each other and be centered around V 1.3.1 Single-Ended Operation Performance with differential input signals is better than with single-ended signals. For this reason, single-ended operation is not ...
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DDC Application Information 3.0 CONTROL INTERFACE The LM97593 is configured by writing control information into 237 control registers within the chip. The contents of these control registers and how to use them are described in section 9.1 Control Register Addresses ...
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DVGA gain step. The LM97593 allows the timing of the gain compensation to be adjusted in the EXT_DELAY regis- ter; see the end of section 6.0 AGC for more ...
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P ranges from Phase dithering can be enabled to reduce the spurious sig- nals created by the NCO due to phase truncation. This trun- cation is unavoidable since the frequency resolution is ...
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GAIN *GAIN 1. The actual gain of the CIC filter will SHIFTUP CIC only be unity for power-of-two decimation values. In other cases the gain will be somewhat less than unity. 4.3 Channel Gain The gain of each channel ...
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FIGURE 27. F2 STD frequency response FIGURE 28. F2 GSM frequency response response through to the second filter. The latter can then be programmed as a Nyquist (typically a root-raised-cosine) filter for matched filtering of digital data. The complete channel ...
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FIGURE 32. CIC, F1, & F2 GSM Passband Flatness decreases relative to the output sample rate, the CIC droop compensation performed by F1 may no longer be required. 4.7 Overall Channel Gain The overall gain of the chip is a ...
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FIGURE 34. Serial output formats. Refer to Figure 13 for detailed timing information rate of 270.833kHz. An OSP starts when a sample is ready and stops when the next one is ready. 5.1 Serial Outputs The LM97593 provides a serial ...
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SCK (or falling edge if the SCK_POL bit in the input control register is set high). Data should be cap- tured on the falling edge of SCK (rising if SCK_POL=1). The chip sends the I ...
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AGC The LM97593 AGC processor monitors the output level of the ADC and servos it to the desired setpoint. The ADC input is controlled by the DVGA to maintain the proper setpoint level. DVGA operation results in a compression ...
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POWER MANAGEMENT The LM97593 can be placed in a low power (static) state by stopping the input clock and setting the PD pin high. To pre- vent this from placing the LM97593 into unexpected states, the SI pin of ...
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Register Name Width Type Default SFS_POL 1b R/W RDY_POL 1b R/W MUX_MODE 1b R/W PACKED 1b R/W Register Name Width Type Default FORMAT 2b R/W FREQ_A 4B R/W PHASE_A 2B R/W FREQ_B 4B R/W PHASE_B 2B R/W A_SOURCE 2 R/W ...
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Register Name Width Type AGC_IC_B 1B R/W AGC_RB_A 1B R AGC_RB_B 1B R TEST_REG 14b R/W Reserved 1B - Register Name Width Type Reserved 1B - DEBUG_EN 1b R/W DEBUG_TAP 5b R/W DITH_A 1b R/W DITH_B 1b R/W AGC_TABLE 32B ...
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Register Name Width Type Default COEF_SEL_F1A 1b R/W COEF_SEL_F1B 1b R/W PAGE_SEL_F1 1b R/W COEF_SEL_F2A 1b R/W COEF_SEL_F2B 1b R/W PAGE_SEL_F2 1b R/W SFS_MODE 1b R/W Default Register Name Width Type SDC_EN 1b R/W AGC_COMB_ORD 2b R/W EXT_DELAY 5b R/W ...
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Register Addr Addr Bit7 Name Hex AGC_IC_A 23 0x17 AgclcA7 AGC_IC_B 24 0x18 AgclcB7 AGC_RB_A 25 0x19 AgcRbA7 AGC_RB_B 26 0x1A AGCRbB7 AGCRbB6 AGCRbB5 AGCRbB4 AGCRbB3 AGCRbB2 AGCRbB1 AGCRbB0 TEST_REG 27 0x1B Test7 28 0x1C DEBUG 31 0x1F DITH_B AGC_TABLE ...
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AGC Theory of Operation A block diagram of the AGC is shown in Figure 40. The DVGA interface comprises four pins for each of the channels. The first three pins of this interface are a 3-bit binary word that controls ...
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F /8, where F is the clock frequency, and the response CK CK magnitude is at least 25dB below the dc value from F 9F /10. Because the 2 nd harmonic from the absolute value CK circuit is about 10dB ...
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FIGURE 42. Example of programmed RAM contents TABLE 5. 15-bit Mixer Output Alignment into the 22-bit SHIFT-UP Based On EXP AGAIN a EXP b Input 000 = -12dB 111 = +0dB -12dB 001 = -6dB 110 = -6dB -12dB 010 ...
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FIGURE 44. AGC integrator output limits www.national.com General Applications Information 10.0 OUTPUTS Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through V ...
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FIGURE 45. Application Circuit 45 30008757 www.national.com ...
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POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF ca- pacitor and with a 0.1 µF ceramic chip capacitor near each power pin. Leadless chip capacitors are preferred because they have low series inductance. ...
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Common Application Pitfalls 15.1 Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted LM97593VH PQFP Package Dimensions 48 ...
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Notes 49 www.national.com ...
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