LM97593VH National Semiconductor, LM97593VH Datasheet - Page 35

• Manufacturer Part Number: LM97593VH
• Description: 12BIT ADC, 2CH, DDC/AGC, 128PQFP
• Manufacturer: National Semiconductor

Specifications of LM97593VH

• Resolution (bits): 12bit
• Input Channel Type: Differential
• Data Interface: Serial
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 1.6V To 2V, 3V To 3.6V
• Supply: RoHS Compliant
• Sampling Rate: 65MSPS
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

6.0 AGC
The LM97593 AGC processor monitors the output level of the
ADC and servos it to the desired setpoint. The ADC input is
controlled by the DVGA to maintain the proper setpoint level.
DVGA operation results in a compression of the signal
through the ADC. The DVGA signal compression is reversed
in the LM97593 to provide > 120dB of linear dynamic range.
This is illustrated in Figure 36.
In order to use the AGC, the DRCS Control Panel software
may be used to calculate the programmable parameters. To
generate these parameters, only the desired setpoint, dead-
band+ hysteresis, and loop time constant need to be supplied.
All subsequent calculations are performed by the software.
Complete details of the AGC operation are provided in an ap-
pendix.
AGC setpoint and deadband are illustrated in Figure 37. The
loop time constant is a measure of how fast the loop will track
FIGURE 36. Output Gain Scaling vs. Input Signal
FIGURE 37. AGC Setup
FIGURE 38. Function controlled by EXT_DELAY register
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a changing signal. Values down to approximately 1.0 mi-
crosecond will be stable with the second order LC noise filter.
Since the DVGA operates with 6dB steps the deadband
should always be greater than 6dB to prevent oscillation. An
increased deadband value will reduce the amount of AGC
operation. A decreased deadband value will increase the
amount of AGC operation but will hold the ADC output closer
to the setpoint. The threshold should be set so that transients
do not cause sustained overrange at the ADC inputs. The
threshold setting can also be used to set the ADC input near
its optimal performance level.
The AGC will free run when AGC_HOLD_IC is set to ‘0’. It
may be set to a fixed gain by setting AGC_HOLD_IC to ‘1’
after programming the desired gain in the AGC_IC_A and
AGC_IC_B registers. Allowing the AGC to free run should be
appropriate for most applications.
Programming the AGC_COMB_ORD register allows the AGC
power detector bandwidth to be reduced if desired. This will
tend to improve the power detector’s ability to reject the signal
carrier frequency and reduce overall AGC activity. Figure 39
shows the power detector response.
The analog gain change from the DVGA must be compen-
sated by the "Float To Fixed" converter after the appropriate
delay. This delay can be adjusted by the EXT_DELAY register
value to make sure the analog gain change is properly com-
pensated in the digital domain.
Figure 38 shows the internal clock latency paths related to the
DVGA and "Float To Fixed" timing conpensation. In this dia-
gram registers are represented by z
delay in ADC clock periods. Following the path from the output
of the AGC integrator through the DVGA, bandpass filter,
ADC and internal register delays adds up to 6 clocks prior to
the "Float To Fixed" converter excluding the bandpass filter
and ADC. Following the path from the AGC integrator to the
"Float To Fixed" is also 6 clocks when EXT_DELAY = 0. The
value programmed in EXT_DELAY should be set to the
pipeline latency of the ADC plus the latency of the bandpass
filter (typically one clock). If ASTROBE and BSTROBE are not
used then subtract one from the resulting total latency.
The LM97593 includes an integrated ADC with a pipeline la-
tency of 7 clocks. Adding one additional clock period for the
bandpass filter requires EXT_DELAY = 7 when the DVGA
ASTROBE and BSTROBE signals are used, otherwise, pro-
gram EXT_DELAY = 6. In most cases ASTROBE and
BSTROBE signals are not used so EXT_DELAY is typically
set to 6.
More accurate time alignment may improve the equalizer /
demodulator performance for EDGE modulated signals and
other signals with a large AM component.
30008758
-N
where N is the sample
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