DSPIC30F2020-20E/SO Microchip Technology, DSPIC30F2020-20E/SO Datasheet - Page 15

• Manufacturer Part Number: DSPIC30F2020-20E/SO
• Description: IC, DSC, 16BIT, 12KB 40MHZ, 5.5V, SOIC28
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F2020-20E/SO

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

43. Module: I
44. Module: I
45. Module: UART (FIFO Error Flags)
© 2008 Microchip Technology Inc.
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register, I2CxRCV, if the lower address
byte
particular, these include all addresses with the
form “XX0000XXXX” and “XX1111XXXX”, with the
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
The lower address byte in 10-bit Addressing mode
should not be a reserved address.
If the I
with an address of 0x102, the I2CxRCV register
content for the lower address byte is 0x01 rather
than
acknowledges both address bytes.
Work around
None.
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO. This has only been observed
when both of the following conditions are met:
• The UART receive interrupt is set to occur
• More than two bytes with an error are received.
In these two circumstances, only the first two bytes
with a parity or framing error will have the
corresponding bits indicated correctly. The error
bits will not be set after this occurs.
Work around
None.
when the FIFO is full or three-quarters full
(U1STA<7:6> = 1x), and
matches
2
C module is configured for a 10-bit slave
0x02.
2
2
C Module
C Module
However,
the
reserved
the
addresses.
I
2
C
module
In
46. Module: Module: PSV Operations
dsPIC30F1010/202X
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher provides the following
command-line switch that implements a work
around for the erratum:
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 toolsuite for further details.
mode) with pre/post decrement
DS80319D-page 15