DSPIC30F2020-20E/SO Microchip Technology, DSPIC30F2020-20E/SO Datasheet - Page 6

• Manufacturer Part Number: DSPIC30F2020-20E/SO
• Description: IC, DSC, 16BIT, 12KB 40MHZ, 5.5V, SOIC28
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F2020-20E/SO

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F1010/202X
7. Module: PWM Jitter
TABLE 1:
EQUATION 2:
EQUATION 3:
DS80319D-page 6
Speed of Operation
The outputs of the PWM module may exhibit a
jitter proportional to the speed of operation of the
device. The jitter may be observed as a deviation
in the PWM Period, Duty Cycle or Phase, and may
be affected independent of each other. As a result,
the maximum deviation exhibited on the PWM
output pin at 30 MIPS is 8.4 nsec.
The jitter is caused by silicon process variations,
noise on the V
temperature of the dsPIC DSC. However, for a
given set of operating conditions, the maximum
jitter will be the same for all three parameters, and
independent of each other.
Table 1 shows the maximum jitter that may be
exhibited at various operating speeds.
The maximum jitter at any operating speed can be
determined using Equation 2.
Where:
• S is the speed of operation in MIPS.
The maximum percentage error observed on the
PWM output can be calculated using Equation 3.
Where:
• x
• x
Work around
Operate the Power Supply PWM module so that
the percentage error in the parameter of interest
(from Equation 3) is within permissible limits of the
application.
Error (%)
Maximum jitter observed (nsec)
interest (PWM period, Duty Cycle or Phase).
parameter of interest (PWM period, Duty Cycle
or Phase).
observed
programmed
30 MIPS
20 MIPS
15 MIPS
=
is the observed value of parameter of
±
is the programmed value of
(
-------------------------------------------------------------- -
x
programmed
DD
x
programmed
rail and the operating
Maximum Jitter on
–
PWM Output
x
observed
12.6 nsec
16.8 nsec
8.4 nsec
=
252
-------- -
S ( )
)
⋅
100
8. Module: ADC Module: Global Software
In order to perform multiple analog-to-digital
conversions using the global software trigger, the
PxRDY bits in the ADSTAT register must be
cleared. The data sheet indicates that the user can
configure the ADC pin pairs to perform a
conversion when the GSWTRG bit in the ADCON
register is set. When the conversion is available,
the user must then clear the GSWTRG bit and set
it again to perform another conversion. Contrary to
what the data sheet indicates, this will not initiate
another conversion unless the PxRDY bits are
cleared. Clearing the PxRDY bits automatically
clears the GSWTRG bit.
This only applies to a polling based approach. If an
interrupt based approach is used, the user is
required to clear the PxRDY bits in the ADC
Interrupt Service Routine (ISR).
Work around
The following sequence should be followed to
manually trigger ADC conversions using the
global software trigger (polling based only.)
1. Set the GSWTRG bit in ADCON to initiate a
2. Check the PxRDY bits to determine when the
3. Clear the PxRDY bits. The GSWTRG bit will be
4. Repeat steps 1 to 3 to perform additional
Alternatively, the individual software trigger can be
selected by setting the TRGSRCx<5:0> bits in the
ADCPCx register equal to 0x01. Instead of using
the global software trigger, the individual software
trigger (ADCPCx<SWTRGx>) bits can be used to
trigger a conversion on a given analog pin pair. In
a bit polling approach, the PENDx in the ADCPCx
register should be used to determine when a
conversion is completed. In an interrupt based
approach, the PxRDY bits get set when the
conversion is complete. This bit must be cleared in
the ADC Interrupt Service Routine in order to
enable future interrupts.
conversion on channels which have the trigger
source as the global software trigger (via the
TRGSRCx<5:0> bits in the ADCPCx
registers).
conversion(s) is completed.
cleared as a result of this operation.
conversions.
Trigger
© 2008 Microchip Technology Inc.