STA333ML STMicroelectronics, STA333ML Datasheet
STA333ML
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STA333ML Summary of contents
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... Order code STA333ML STA333ML13TR February 2010 Description STA333ML is a single die embedding digital audio processing and high-efficiency power amplification, capable of operating without the aid of an external microcontroller. The STA333ML is part of the Sound Terminal™ family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment ...
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... Oversampling selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 Gain selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.7 Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 PLL filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 Doc ID 13177 Rev 5 STA333ML ...
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... STA333ML 1 Block diagram Figure 1. Block diagram interface Volume control PLL Protection current/thermal Logic Power control DDX Regulators Bias Doc ID 13177 Rev 5 Block diagram Channel 1A Channel 1B Channel 2A Channel 2B 3/20 ...
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... Power negative supply Power Power positive supply Out Output half bridge 2A Out Output half bridge 1B Doc ID 13177 Rev 5 36 VDD_DIG 35 GND_DIG 34 GAIN 33 ONSEL 32 INT_LINE 31 RESET 30 SDI 29 LRCKI 28 BICKI 27 XTI 26 GND_PLL 25 FILTER_PLL VDD_PLL 24 PWRDN 23 GND_DIG 22 21 VDD_DIG 20 N.C. 19 N.C. Description 2 S format - 3 reference CC STA333ML ...
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... STA333ML Table 2. Pin description (continued) Pin 11 VCC1 12 GND1 13 OUT1A 14 GND_REG 15 VDD_REG 16 CONFIG 17 N.C. 18 N.C. 19 N.C. 20 N.C. 21 VDD_DIG 22 GND_DIG 23 PWRDN 24 VDD_PLL 25 FILTER_PLL 26 GND_PLL 27 XTI 28 BICKI 29 LRCKI 30 SDI 31 RESET 32 INT_LINE 33 ONSEL 34 GAIN 35 GND_DIG 36 VDD_DIG - EP Name Type Power Power positive supply Gnd Power negative supply ...
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... Power supply voltage (pins VCC1, VCC2 Logic input interface L V Digital supply (pin VDD_DIG Ambient temperature amb 6/20 Parameter - -0 -40 Parameter 140 18 Parameter 4.5 2.7 2.7 0 Doc ID 13177 Rev 5 STA333ML Min Typ Max Unit - 150 °C - 150 °C Min Typ Max Unit 1.5 2 °C/W ...
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... STA333ML 3.4 Electrical specifications - digital section Table 6. Electrical specifications for digital section Symbol I Input current without bias il device Low level input voltage il V High level input voltage ih V Low level output voltage ol V High level output voltage oh I Pull-up/down current pu Equivalent pull-up/down ...
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... Internal clock = 49.152 MHz - Hi-Z output - No load - A-weighted kHz DDX stereo, <5 kHz Vripple = 1 V RMS Audio input = dither only DDX stereo, <5 kHz One chan. driven other channel measured into - Doc ID 13177 Rev 5 STA333ML Min Typ Max 0.03 0.06 0 2.7 3.8 5 ...
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... STA333ML 3.6 Power on sequence Figure 3. Power-on sequence VCC VCC VCC VCC VDD_Dig VDD_Dig VDD_Dig VDD_Dig XTI XTI XTI XTI Reset Reset Reset Reset PWDN PWDN PWDN PWDN TR = minimum time between XTI master clock stable and reset removal Note 1: clock stable means: f Note 2: No specific V 3 ...
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... Serial audio interface protocols The STA333ML serial audio input interfaces with standard digital audio components and accepts serial data formats. The STA333ML always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28), and serial data SDI (pin 30) ...
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... If so the channel is muted. 4.4 Fade-in/out feature The STA333ML has internal fade-in / fade-out feature when powered on or off, or after a fault condition. 4.5 Oversampling selector Pin ONSEL (33) is used to configure the PLL to accept 256 * fs or 384 * fs master clock. ...
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... Applications schematic Figure 8 below shows the schematic of a typical application for the STA333ML. Concerning the power supplies, take care when designing the PCB layout. In particular, the 3.3-Ω resistors on the digital supplies (VDD_DIG) must be placed as close as possible to the device. This helps to prevent parasitic oscillation in the digital part of the device due to the inductive tracks of the PCB ...
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... STA333ML 5.2 Internal voltage reference An embedded voltage regulator produces the reference voltages for the DMOS bridge driver. It requires two 100 nF capacitors to keep the regulator stable. The capacitors should be place close to the pins. Figure 9. Reference voltage block diagram VCC_REG 100 nF VSS_REG VDD_REG ...
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... BTL stereo mode. 22 µH 100 nF 100 nF 22R 6R2 100 nF 330 pF 6R2 100 nF 22 µH 22 µH 100 nF 100 nF 22R 6R2 100 nF 330 pF 6R2 100 nF 22 µH Doc ID 13177 Rev 5 STA333ML 470 nF Left 470 nF Right ...
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... STA333ML Figure 12. Filterless output configuration OUT1A OUT1B OUT2A OUT2B The filterless application is more critical in terms of EMI quite important to follow the below suggestion: Tracks from amplifier to speaker should be as short as possible. Ferrite beads can be used (instead of coils) to improve EMI performance. – Ferrite beads must have a low impedance in the audio band and high impedance at high frequencies. – ...
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... Using a double layer PCB the thermal resistance junction to ambient with 2 copper ground areas The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. The max estimated dissipated power for the STA333ML is into 8 Ω Figure 13. Double layer PCB with 2 copper ground areas and 16 via holes Figure 14 ...
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... STA333ML 7 Package mechanical data Figure 15 shows the package outline and Figure 15. PowerSSO-36 EPD outline drawing Table 8 gives the dimensions. Doc ID 13177 Rev 5 Package mechanical data 17/20 ...
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... Doc ID 13177 Rev 5 STA333ML Dimensions in inches Min Typ 0.085 - 0.097 0.085 - 0.094 0.00 - 0.004 0.007 - 0.014 0.009 - 0.013 0.398 - 0.413 0.291 - 0.299 - 0.020 - - 0.335 - - 0.091 - - - 0.004 0.398 - 0 ...
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... STA333ML 8 Revision history Table 9. Document revision history Date 1-Feb-2007 2-May-2008 4-Nov-2008 28-Jan-2010 3-Feb-2010 Revision 1 Initial release. 2 Package information update Added Table 6: Electrical specifications for digital section on page 7 Updated Table 7: Electrical specifications for power section on page 7 Added Section 3.6: Power on sequence on page 9 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 20/20 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 13177 Rev 5 STA333ML ...