ADSP-TS201SABPZ060 Analog Devices Inc, ADSP-TS201SABPZ060 Datasheet
ADSP-TS201SABPZ060
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ADSP-TS201SABPZ060 Summary of contents
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... REGISTER 128 128 FILE DAB DAB 32-BIT × 32-BIT COMPUTATIONAL BLOCKS Figure 1. Functional Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 TigerSHARC Embedded Processor ADSP-TS201S Table 1) JTAG PORT SOC BUS 6 JTAG EXTERNAL PORT HOST ...
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... Filtering Reference Voltage and Clocks .................... 10 Development Tools ............................................. 10 Evaluation Kit .................................................... 11 Designing an Emulator-Compatible DSP Board (Target) .......................................... 11 Additional Information ........................................ 11 Pin Function Descriptions ....................................... 12 Strap Pin Function Descriptions ................................ 20 ADSP-TS201S—Specifications .................................. 21 Operating Conditions .......................................... 21 Electrical Characteristics ....................................... 22 Package Information ........................................... 23 Absolute Maximum Ratings .................................. 23 ESD Sensitivity ................................................... 23 Timing Specifications .......................................... 24 General AC Timing .......................................... 24 Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing ................ 30 Link Port— ...
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... I/O access and provide 33.6G bytes per second of internal memory bandwidth. Operating at 600 MHz, the ADSP-TS201S processor’s core has a 1.67 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the ADSP-TS201S processor can perform 4.8 billion, 40-bit MACS or 1.2 billion, 80-bit MACS per second. shows the DSP’ ...
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... FIR filters. DUAL INTEGER ALU (IALU) The ADSP-TS201S processor has two IALUs that provide pow- erful address generation capabilities and perform many general- purpose integer operations. The IALUs are referred and K in assembly syntax and have the following features: • ...
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... The ADSP-TS201S processor internal memory has 24M bits of on-chip DRAM memory, divided into six blocks of 4M bits (128K words × 32 bits). Each block—M0, M2, M4, M6, M8, and M10— ...
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... Program access of all memory as 32-, 64-, or 128-bit words—16-bit words with the DAB EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE) The ADSP-TS201S processor’s external port provides the DSP’s interface to off-chip memory and peripherals. The 4G word address space is included in the DSP’s unified address space. GLOBAL SPACE ...
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... HBG and relinquishes the external bus. The host can directly read or write the internal memory of the ADSP-TS201S processor, and it can access most of the DSP reg- isters, including DMA control (TCB) registers. Vector interrupts support efficient execution of host commands. ...
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... SDA10 CONTROLIMP1–0 CONTROL DS2–0 JTAG Figure 4. ADSP-TS201S Shared Memory Multiprocessing System During a transaction, the DSP relinquishes the external data bus; outputs addresses and memory selects (MSSD3–0); outputs the IORD, IOWR, IOEN, and RD/WR strobes; and responds to ACK. • DMA chaining. DMA chaining operations enable applica- tions to automatically link one DMA transfer sequence to another for continuous transmission ...
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... Memory) IRQ3 0x0000 0000 (Internal Memory) The ADSP-TS201S processor core always exits from reset in the idle state and waits for an interrupt. Some of the interrupts in the interrupt vector table are initialized and enabled after reset. For more information on boot options, see the EE-200: ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Oper- ation on the Analog Devices website (www ...
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... IF CLOCK DRIVER VOLTAGE > V DD_IO Figure 7. SCLK_V Filtering Scheme REF DEVELOPMENT TOOLS The ADSP-TS201S processor is supported with a complete set ®† of CROSSCORE software and hardware development tools, including Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP-TS201S processor ...
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... Analog Devices DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-TS201S processor to monitor and con- trol the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modifi- cation of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’ ...
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... ADSP-TS201S PIN FUNCTION DESCRIPTIONS While most of the ADSP-TS201S processor’s input pins are nor- mally synchronous—tied to a specific clock—a few are asynchronous. For these asynchronous signals, an on-chip syn- chronization circuit prevents metastability problems. Use the ac specification for asynchronous signals when the system design requires predictable, cycle-by-cycle behavior for these signals. Table 3. Pin Definitions— ...
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... RD. RD changes concurrently with ADDR pins. 1 epu Write Low. WRL is asserted in two cases: when the ADSP-TS201S processor writes to an even address word of external memory or to another external bus agent; and when the ADSP-TS201S processor writes to a 32-bit zone (host, memory, or DSP programmed to 32-bit bus). An external master (host or DSP) asserts WRL for writing to a DSP’ ...
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... ADSP-TS201S Table 6. Pin Definitions—External Port Arbitration Signal Type BR7–0 I/O ID2–0 I (pd BOFF I BUSLOCK O/T (pu_0) HBR I HBG I/O/T (pu_0) CPA I/O/OD (pu_od_0) DPA I/O/OD (pu_od_0 input asynchronous output open-drain output three-state power supply ground internal pull-down Ω ...
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... Active on flyby transactions. Ω on DSP pu_0 = internal pull- Ω on DSP bus master; pu_m = internal pull- Electrical Characteristics on Page DD_IO Rev Page December 2006 ADSP-TS201S Ω on DSP pu_od_0 = internal Ω on DSP bus master; pu_ad 22. Ω epu = external pull-up approx- ...
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... ADSP-TS201S Table 8. Pin Definitions—External Port SDRAM Controller Signal Type MSSD3–0 I/O/T (pu_0) RAS I/O/T (pu_0) CAS I/O/T (pu_0) LDQM O/T (pu_0) HDQM O/T (pu_0) SDA10 O/T (pu_0) SDCKE I/O/T (pu_m/ pd_m) SDWE I/O/T (pu_0 input asynchronous output open-drain output three-state power supply ground internal pull-down Ω ...
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... For more information, see Table 16 on Page Ω on DSP pu_0 = internal pull- Ω on DSP bus master; pu_m = internal pull- Electrical Characteristics on Page DD_IO Rev Page December 2006 ADSP-TS201S Ω on DSP pu_od_0 = internal Ω on DSP bus master; pu_ad 22. Ω epu = external pull-up approx- ...
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... ADSP-TS201S Table 11. Pin Definitions—Link Ports Signal Type LxDATO3–0P O LxDATO3–0N O LxCLKOUTP O LxCLKOUTN O LxACKI I (pd) LxBCMPO O (pu) LxDATI3–0P I LxDATI3–0N I LxCLKINP I/A LxCLKINN I/A LxACKO O LxBCMPI I (pd_l input asynchronous output open-drain output three-state power supply ground internal pull-down Ω ...
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... These pins are reserved and must be left unconnected. Ω on DSP pu_0 = internal pull- Ω on DSP bus master; pu_m = internal pull- Electrical Characteristics on Page DD_IO Rev Page December 2006 ADSP-TS201S Ω on DSP pu_od_0 = internal Ω on DSP bus master; pu_ad 22. Ω epu = external pull-up approx- ...
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... ADSP-TS201S STRAP PIN FUNCTION DESCRIPTIONS Some pins have alternate functions at reset. Strap options set DSP operating modes. During reset, the DSP samples the strap option pins. Strap pins have an internal pull-up or pull-down for the default value strap pin is not connected to an over- driving external pull-up, pull-down, or logic load, the DSP samples the default value during reset ...
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... TDI, TMS, TRST, CIMP1–0, ID2–0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3–0, CPA, DPA, DMAR3–0. IH2 5 Applies to input and bidirectional pins. 6 For details on internal and external power calculation issues, including other operating conditions, see the EE-170, Estimating Power for the ADSP-TS201S on the Analog Devices website. 30. Test Conditions @ CCLK = 600 MHz ...
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... ADSP-TS201S Table 18. Maximum Duty Cycle for Input Transient Voltage Max (V) V Min ( +3.63 –0.33 +3.64 –0.34 +3.70 –0.40 +3.78 –0.48 +3.86 –0.56 +3.93 –0.63 1 The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of ...
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... PACKAGE INFORMATION The information presented in Figure 8 provide details about the package branding for the ADSP-TS201S processors. For a com- plete listing of product availability, see Ordering Guide on Page 46. a ADSP-TS20xS tppZ-ccc LLLLLLLLL-L 2.0 yyww country_of_origin T Figure 8. Typical Package Brand Table 19. Package Brand Information ...
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... FLAG3–0 (input only) pins, all ac timing for the ADSP-TS201S processor is relative to a reference clock edge. Because input setup/hold, output valid/hold, and output enable/disable times are relative to a clock edge, the timing data for the ADSP- TS201S processor has few calculated (formula-based) values. For information on ac timing, see ...
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... SCLKH SCLKL Figure 10. Reference Clocks—System Clock (SCLK) Cycle Time t TCK t t TCKH TCKL Figure 11. Reference Clocks—JTAG Test Clock (TCK) Cycle Time Rev Page December 2006 ADSP-TS201S Max Min Max 0.60 × t 0.45 × t 0.55 × t SCLK SCLK SCLK 0.60 × ...
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... ADSP-TS201S 1 Table 25. Power-Up Timing Parameter Timing Requirement t V Stable After V VDD_DRAM DD_DRAM DD 1 For information about power supply sequencing and monitoring solutions, please visit www.analog.com/sequencing DD_A V DD_IO V DD_DRAM Table 26. Power-Up Reset Timing Parameter Timing Requirements t RST_IN Deasserted After V RST_IN_PWR Strap Pins Stable ...
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... Table 28. On-Chip DRAM Refresh Parameter Timing Requirement t On-chip DRAM Refresh Period REF 1 For more information on setting the refresh rate for the on-chip DRAM, refer to the ADSP-TS201 TigerSHARC Processor Programming Reference. t RST_IN t RST_OUT t STRAP Figure 14. Normal Reset Timing Rev Page December 2006 ...
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... ADSP-TS201S Table 29. AC Signal Specifications (All values in this table are in nanoseconds.) Name Description ADDR31–0 External Address Bus DATA63–0 External Data Bus MSH Memory Select HOST Line MSSD3–0 Memory Select SDRAM Lines MS1–0 Memory Select for Static Blocks ...
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... DD_IO 1.25V SCLK TCK INPUT 1.25V SETUP OUTPUT 1.25V VALID OUTPUT DISABLE Figure 15. General AC Parameters Timing Rev Page December 2006 ADSP-TS201S — — — — — — — — — — — — — — — — — — — SCLK +12.0 – ...
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... ADSP-TS201S Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing Table 30 and Table 31 with Figure 16 provide the electrical characteristics for the LVDS link ports. The LVDS link port sig- nal definitions represent all differential signals with a V level and use signal naming without N (negative) and P (posi- ...
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... LCR × t CCLK 23) 0. the core period. specification on output period must be considered. COJT . For a 1-bit link × LCR × t CCLK Rev Page December 2006 ADSP-TS201S Max 350 350 Smaller of 12.5 or 1.1 × LCR × CCLK 0.6 × t LCLKOP 0.6 × t LCLKOP ± ...
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... ADSP-TS201S t LCLKOP LxCLKOUT t LCLKOH t COJT Figure 18. Link Ports—Output Clock V O_P C L_P O_N C L_N t REO | | + V MIN MIN OD Figure 19. Link Ports—Differential Output Signals Transition Time LxCLKOUT LxDATO LxACKI LxBCMPO LxCLKOUT V t LCLKOL 100 0.1pF 5pF L_P 1 These parameters are valid for both clock edges. ...
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... OD LxDATO LxACKI LxBCMPO Figure 22. Link Ports—Transmission End and Stops LxCLKOUT LxDATO LxACKI Figure 23. Link Ports—Back to Back Transmission Rev Page December 2006 LAST EDGE IN A QUAD WORD t LACKIS t BCMPOH LAST EDGE IN A QUAD WORD t t LACKIS ADSP-TS201S t LACKIH LACKIH ...
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... ADSP-TS201S Link Port—Data In Timing Table 33 with Figure 24 and Figure 25 provide the data in timing for the LVDS link ports. Table 33. Link Port—Data In Timing Parameter Description Inputs t LxCLKIN Period (Figure LCLKIP t LxDATI Input Setup LDIS t LxDATI Input Hold (Figure LDIH t LxBCMPI Setup ...
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... LxCLKIN LDIS LDIH LDIS LxDATI Figure 25. Link Ports—Data Input Setup and Hold 1 These parameters are valid for both clock edges. t LCLKIP t LDIH 1 Rev Page December 2006 ADSP-TS201S ...
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... Figure 33 show typical I–V characteristics for the output drivers of the ADSP-TS201S processor. The curves in these diagrams represent the current drive capability of the out- put drivers as a function of output voltage over the range of drive strengths. Typical drive currents for intermediate temper- atures (such as 85° ...
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... I OH REFERENCE 2.4 2.8 SIGNAL V OH (MEASURED (MEASURED) = 2.63V, –40°C = 2.63V, –40° 2.4 2.8 Rev Page December 2006 ADSP-TS201S 28. These include output disable time, output 1.25V . This decay time can be approximated by the fol Δ ⁄ DECAY the difference between ...
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... ADSP-TS201S Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv- ing. The time for the voltage on the bus to ramp by ΔV is dependent on the capacitive load and the drive current, I ...
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... Strength 0.0474x + 1.0806 Strength 0.0345x + 1.2329 Strength 0.0296x + 1.2064 Strength 0.0246x + 1.0944 Strength 0.0187x + 1.1005 Strength 0.0156x + 1.084 RISE TIME Y = 0.0377 x + 0.7449 80 90 100 = 2.5 V) DD_IO Rev Page December 2006 ADSP-TS201S STRENGTH 2.5V) DD_IO RISE TIME Y = 0.0321 x + 0.6512 FALL TIME 0.0313x + 0.818 ...
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... The ADSP-TS201S processor is rated for performance under T environmental conditions specified in the CASE ditions on Page 21. Thermal Characteristics The ADSP-TS201S processor is packaged × 25 mm, thermally enhanced ball grid array (BGA_ED). The ADSP-TS201S processor is specified for a case temperature ( ensure that the T data sheet specification is not CASE CASE exceeded, a heat sink and/or an air flow source may be required ...
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... BGA_ED package and Table 35 assignments For a more detailed pin summary diagram, see the EE-179: ADSP-TS201S System Design Guidelines on the Analog Devices website (www.analog.com). lists the signal-to-ball TOP VIEW Figure 46. 576-Ball BGA_ED Pin Configurations Rev Page December 2006 ADSP-TS201S KEY: SIGNAL DD_IO V DD_DRAM V DD_A ...
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... ADSP-TS201S Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments Ball No. Signal Name Ball No. Signal Name DATA51 DATA49 B4 A5 DATA43 B5 A6 DATA41 B6 A7 DATA37 B7 A8 DATA33 B8 A9 DATA29 B9 A10 DATA25 B10 A11 DATA23 B11 A12 DATA19 B12 A13 DATA15 B13 A14 DATA11 ...
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... R17 R18 V DD_DRAM DD_DRAM V R19 V DD_DRAM DD_DRAM V R20 V DD_IO DD_IO L0DATO1_N R21 NC L0DATO1_P R22 V SS L0DATO0_N R23 L0BCMPO L0DATO0_P R24 L0ACKI Rev Page December 2006 ADSP-TS201S Ball No. Signal Name M1 BR3 M2 SCLKRAT1 M3 BR5 M4 BR6 M5 V DD_IO M10 V SS M11 V SS M12 V SS ...
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... L1DATO0_P AB24 1 On revision 1.x silicon, the R2 and R3 balls are NC. On revision 0.x silicon, the R2 ball is SCLK, and the R3 ball is SCLK_V on revision 0.x silicon, see the EE-179: ADSP-TS20x TigerSHARC System Design Guidelines on the Analog Devices website (www.analog.com). Ball No. Signal Name MSSD2 W1 ...
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... OUTLINE DIMENSIONS The ADSP-TS201S processor is available × 25 mm, 576-ball metric thermally enhanced ball grid array (BGA_ED) package with 24 rows of balls (BP-576). 1.25 A1 BALL 1.00 INDICATOR 0.75 1.25 1.00 0.75 TOP VIEW 3.10 2.94 2.78 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. THE ACTUAL POSITION OF THE BALL ITHIN 0. ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES ...
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... Temperature 1 Model Range ADSP-TS201SABP-060 –40°C to +85°C ADSP-TS201SABP-050 –40°C to +85°C ADSP-TS201SYBP-050 –40°C to +105°C 500 MHz 3 ADSP-TS201SABPZ060 –40°C to +85°C 3 ADSP-TS201SABPZ050 –40°C to +85°C 3 ADSP-TS201SYBPZ050 –40°C to +105°C 500 MHz 1 Represents case temperature. 2 The instruction rate is the same as the internal processor core clock (CCLK) rate. ...
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... Rev Page December 2006 ADSP-TS201S ...
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... ADSP-TS201S ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04324-0-11/06(C) Rev Page December 2006 ...