ADSP-TS201SABPZ060 Analog Devices Inc, ADSP-TS201SABPZ060 Datasheet - Page 13

• Manufacturer Part Number: ADSP-TS201SABPZ060
• Description: IC, FLOAT-PT DSP, 64BIT, 600MHZ, BGA-576
• Manufacturer: Analog Devices Inc
• Series: TigerSHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-TS201SABPZ060

• Frequency: 600MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: HPI
• No. Of I/o's: 4
• Supply Voltage Range: 1.14V To 1.26V, 2.38V To 2.63V
• Interface: Host Interface, Link Port, Multi-Processor
• Clock Rate: 600MHz
• Non-volatile Memory: External
• On-chip Ram: 3MB
• Voltage - I/o: 2.50V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 576-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-TS201S-EZLITE - KIT LITE EVAL FOR ADSP-TS201S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 5. Pin Definitions—External Port Bus Controls
1
Signal
ADDR31–0
DATA63–0
RD
WRL
WRH
ACK
BMS
MS1–0
MSH
BRST
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5 k
pull-up 500
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
This external pull-up may be omitted for the ID = 000 TigerSHARC processor.
Ω
; pu = internal pull-up 5 k
Ω
Ω
to V
on DSP ID = 0; pd_m = internal pull-down 5 k
DD_IO
, nc = not connected; na = not applicable (always used); V
Ω
. For more pull-down and pull-up information, see
Type
I/O/T
(pu_ad)
I/O/T
(pu_ad)
I/O/T
(pu_0)
I/O/T
(pu_0)
I/O/T
(pu_0)
I/O/T/OD
(pu_od_0)
O/T
(pu_0)
O/T
(pu_0)
O/T
(pu_0)
I/O/T
(pu_0)
Ω
; pd_0 = internal pull-down 5 k
Term
nc
nc
epu
epu
epu
epu
na
nc
nc
epu
1
1
1
1
1
Rev. C | Page 13 of 48 | December 2006
Description
Address Bus. The DSP issues addresses for accessing memory and peripherals on
these pins. In a multiprocessor system, the bus master drives addresses for accessing
internal memory or I/O processor registers of other ADSP-TS201S processors. The DSP
inputs addresses when a host or another DSP accesses its internal memory or I/O
processor registers.
External Data Bus. The DSP drives and receives data and instructions on these pins.
Pull-up or pull-down resistors on unused DATA pins are unnecessary.
Memory Read. RD is asserted whenever the DSP reads from any slave in the system,
excluding SDRAM. When the DSP is a slave, RD is an input and indicates read trans-
actions that access its internal memory or universal registers. In a multiprocessor
system, the bus master drives RD. RD changes concurrently with ADDR pins.
Write Low. WRL is asserted in two cases: when the ADSP-TS201S processor writes to
an even address word of external memory or to another external bus agent; and when
the ADSP-TS201S processor writes to a 32-bit zone (host, memory, or DSP
programmed to 32-bit bus). An external master (host or DSP) asserts WRL for writing
to a DSP’s low word of internal memory. In a multiprocessor system, the bus master
drives WRL. WRL changes concurrently with ADDR pins. When the DSP is a slave, WRL
is an input and indicates write transactions that access its internal memory or
universal registers.
Write High. WRH is asserted when the ADSP-TS201S processor writes a long word
(64 bits) or writes to an odd address word of external memory or to another external
bus agent on a 64-bit data bus. An external master (host or another DSP) must assert
WRH for writing to a DSP’s high word of 64-bit data bus. In a multiprocessing system,
the bus master drives WRH. WRH changes concurrently with ADDR pins. When the
DSP is a slave, WRH is an input and indicates write transactions that access its internal
memory or universal registers.
Acknowledge. External slave devices can deassert ACK to add wait states to external
memory accesses. ACK is used by I/O devices, memory controllers, and other periph-
erals on the data phase. The DSP can deassert ACK to add wait states to read and write
accesses of its internal memory. The pull-up is 50 Ω on low-to-high transactions and
is 500 Ω on all other transactions.
Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During
reset, the DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. In a multipro-
cessor system, the DSP bus master drives BMS. For details, see
Page 9
Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0
or 1, respectively. MS1–0 are decoded memory address pins that change concurrently
with ADDR pins. When ADDR31:27 = 0b00110, MS0 is asserted. When ADDR31:27 =
0b00111, MS1 is asserted. In multiprocessor systems, the master DSP drives MS1–0.
Memory Select Host. MSH is asserted whenever the DSP accesses the host address
space (ADDR31 = 0b1). MSH is a decoded memory address pin that changes concur-
rently with ADDR pins. In a multiprocessor system, the bus master DSP drives MSH.
Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading
or writing data associated with consecutive addresses. A slave device can ignore
addresses after the first one and increment an internal address counter after each
transfer. For host-to-DSP burst accesses, the DSP increments the address automati-
cally while BRST is asserted.
Ω
Ω
on DSP bus master; pu_m = internal pull-up 5 k
and the EBOOT signal description in
on DSP ID = 0; pu_0 = internal pull-up 5 k
Electrical Characteristics on Page
DD_IO
= connect directly to V
Table 16 on Page
Ω
to V
Ω
on DSP ID = 0; pu_od_0 = internal
SS
DD_IO
; epu = external pull-up approx-
22.
Ω
; V
on DSP bus master; pu_ad
SS
= connect directly to V
ADSP-TS201S
20.
Reset and Booting on
SS