ADSP-TS201SABPZ060 Analog Devices Inc, ADSP-TS201SABPZ060 Datasheet - Page 44

• Manufacturer Part Number: ADSP-TS201SABPZ060
• Description: IC, FLOAT-PT DSP, 64BIT, 600MHZ, BGA-576
• Manufacturer: Analog Devices Inc
• Series: TigerSHARCr
• Type: Fixed/Floating Pointr

Specifications of ADSP-TS201SABPZ060

• Frequency: 600MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: HPI
• No. Of I/o's: 4
• Supply Voltage Range: 1.14V To 1.26V, 2.38V To 2.63V
• Interface: Host Interface, Link Port, Multi-Processor
• Clock Rate: 600MHz
• Non-volatile Memory: External
• On-chip Ram: 3MB
• Voltage - I/o: 2.50V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 576-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-TS201S-EZLITE - KIT LITE EVAL FOR ADSP-TS201S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-TS201S
Table 35. 576-Ball (25 mm × 25 mm) BGA_ED Ball Assignments (Continued)
1
Ball No. Signal Name
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
On revision 1.x silicon, the R2 and R3 balls are NC. On revision 0.x silicon, the R2 ball is SCLK, and the R3 ball is SCLK_V
on revision 0.x silicon, see the EE-179: ADSP-TS20x TigerSHARC System Design Guidelines on the Analog Devices website (www.analog.com).
MSSD0
RST_OUT
ID2
DS1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
L1CLKINN
L1CLKINP
L1DATI1_N
L1DATI1_P
FLAG2
FLAG1
IRQ3
V
IRQ0
IOEN
DMAR0
HBR
L3BCMPO
L3DATO1_N
L3DATO3_N
V
L3DATI2_N
L3DATI1_N
NC
L2DATO0_N
L2CLKON
L2DATO3_N
L2CLKINN
L2DATI1_N
V
L1BCMPO
L1DATO0_N
L1DATO0_P
DD_IO
DD
DD
SS
SS
DD
DD_DRAM
SS
SS
SS
SS
SS
SS
DD
DD
DD_IO
SS
SS
SS
V1
V2
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V23
V24
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB12
AB13
AB14
AB17
AB19
AB20
AB21
AB22
Ball No. Signal Name
V3
V4
V21
V22
AB1
AB2
AB11
AB15
AB16
AB18
AB23
AB24
MSSD2
DS2
POR_IN
CONTROLIMP1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
L1DATI3_N
L1DATI3_P
L1DATI2_N
L1DATI2_P
V
V
V
NC
IRQ2
IRQ1
DMAR1
HBG
L3ACKI
L3DATO1_P
L3DATO3_P
V
L3DATI2_P
L3DATI1_P
V
L2DATO0_P
L2CLKOP
L2DATO3_P
L2CLKINP
L2DATI1_P
L2ACKO
V
V
V
SS
DD
DD
DD
DD
DD
DD_DRAM
DD_DRAM
DD
DD
DD_DRAM
DD_DRAM
DD
DD
DD
DD_IO
SS
SS
SS
SS
SS
SS
DD_IO
DD_IO
Rev. C | Page 44 of 48 | December 2006
Ball No. Signal Name
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
L3DATI0_N
L2DATI2_N
CONTROLIMP0
ENEDREG
TDI
TDO
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
L1CLKON
L1CLKOP
L1DATO3_N
L1DATO3_P
FLAG0
V
V
TMS
IOWR
DMAR2
CPA
BOFF
L3DATO0_N
L3CLKON
L3DATO2_N
L3DATI3_N
L3CLKINN
L3ACKO
L2BCMPO
L2DATO1_N
L2DATO2_N
L2DATI3_N
L2DATI0_N
V
V
L1ACKI
DD_IO
DD
DD
DD
DD
DD
DD_DRAM
DD_DRAM
DD
DD
DD_DRAM
DD_DRAM
DD
DD
DD
DD_IO
SS
DD_IO
DD_IO
SS
REF
. For more information on SCLK and SCLK_V
Ball No. Signal Name
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
EMU
TCK
TMR0E
FLAG3
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
L1DATO1_N
L1DATO1_P
L1DATO2_N
L1DATO2_P
V
ID1
V
TRST
IORD
DMAR3
DPA
BUSLOCK
L3DATO0_P
L3CLKOP
L3DATO2_P
L3DATI3_P
L3CLKINP
L3DATI0_P
L3BCMPI
L2ACKI
L2DATO1_P
L2DATO2_P
L2DATI3_P
L2DATI2_P
L2DATI0_P
V
L2BCMPI
V
SS
DD_IO
SS
DD_IO
SS
DD_IO
DD_IO
DD_IO
DD_IO
DD_IO
DD_IO
SS
DD_IO
SS
DD_IO
SS
SS
DD_IO
DD_IO
SS
REF