EPM7256AEFC256-10N Altera, EPM7256AEFC256-10N Datasheet - Page 41

IC PLD EEPROM 256 MACROCELL FBGA-256

EPM7256AEFC256-10N

Manufacturer Part Number
EPM7256AEFC256-10N
Description
IC PLD EEPROM 256 MACROCELL FBGA-256
Manufacturer
Altera
Series
MAX 7000AEr
Datasheet

Specifications of EPM7256AEFC256-10N

Cpld Type
EEPROM
No. Of Macrocells
256
No. Of I/o's
164
Propagation Delay
10ns
Global Clock Setup Time
3.9ns
Frequency
172.4MHz
Supply Voltage Range
3V To 3.6V
Family Name
MAX 7000A
Memory Type
EEPROM
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7256AEFC256-10N
Manufacturer:
ALTERA
0
Part Number:
EPM7256AEFC256-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM7256AEFC256-10N
0
Altera Corporation
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Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
Table 22. EPM7128AE Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = on
V
Output buffer disable delay C1 = 5 pF
Register setup time
Register hold time
Register setup time of fast
input
Register hold time of fast
input
Register delay
Combinatorial delay
Array clock delay
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
Conditions
MAX 7000A Programmable Logic Device Data Sheet
Min
1.4
0.6
1.1
1.4
-5
Max
0.7
0.7
2.5
2.0
0.4
1.6
0.7
0.0
0.8
1.3
5.8
4.0
4.5
9.0
4.0
0.8
0.5
1.2
Note (1)
Speed Grade
Min
2.1
1.0
1.6
1.4
-7
Max
1.0
1.0
3.0
2.9
0.7
2.4
1.0
0.0
1.2
1.7
6.2
4.0
4.5
9.0
4.0
1.2
0.9
1.7
Min
2.9
1.3
1.6
1.4
-10
Max
10.0
1.3
1.4
1.4
3.4
3.8
0.9
3.1
0.0
1.6
2.1
6.6
5.0
5.5
5.0
1.6
1.3
2.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41

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