74HC164N NXP Semiconductors, 74HC164N Datasheet - Page 2

• Manufacturer Part Number: 74HC164N
• Description: IC, 74HC CMOS LOGIC
• Manufacturer: NXP Semiconductors

Specifications of 74HC164N

• No. Of Elements: 1
• Ic Output Type: Standard
• Logic Case Style: DIP
• No. Of Pins: 14
• Supply Voltage Range: 2V To 6V
• Operating Temperature Range: -40°C To +125°C
• Svhc: No SVHC (18-Jun-2010)
• Logic Type: Shift Register
• Shift Register Function: Serial To Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT164 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT164 are 8-bit edge-triggered shift registers
with serial data entry and an output from each of the eight
stages.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
f
C
C
PHL
max
Gated serial data inputs
Asynchronous master reset
Output capability: standard
I
8-bit serial-in/parallel-out shift register
I
PD
CC
f
f
C
V
For HCT the condition is V
SYMBOL
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
2
= 25 C; t
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per
package
V
f
CP to Q
MR to Q
o
CC
) = sum of outputs
2
f
r
i
n
= t
n
PARAMETER
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
C
notes 1 and 2
L
2
.
= 15 pF; V
CONDITIONS
Data is entered serially through one of two inputs (D
D
data entry through the other input.
Both inputs must be connected together or an unused
input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH
transition of the clock (CP) input and enters into Q
is the logical AND of the two data inputs (D
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all
other inputs and clears the register asynchronously,
forcing all outputs LOW.
sb
D
); either input can be used as an active HIGH enable for
in W):
CC
= 5 V
12
11
78
3.5
40
HC
TYPICAL
74HC/HCT164
14
16
61
3.5
40
Product specification
HCT
sa
,D
sb
ns
ns
MHz
pF
pF
) that
0
UNIT
, which
sa
or