SST25VF040B-50-4I-QAF SILICON STORAGE TECHNOLOGY, SST25VF040B-50-4I-QAF Datasheet - Page 17

• Manufacturer Part Number: SST25VF040B-50-4I-QAF
• Description: 4M FLASH MEMORY, SPI EEPROM, WSON-8
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF040B-50-4I-QAF

• Memory Size: 4Mbit
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: WSON
• No. Of Pins: 8
• Svhc: No SVHC (18-Jun-2010)
• Device: RoHS Compliant
• Package / Case: WSON
• Memory Type: Flash
• Memory Configuration: 512K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes

4 Mbit SPI Serial Flash
SST25VF040B
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to 1 allowing Write
operations to occur. The WREN instruction must be exe-
cuted prior to any Write (Program/Erase) operation. The
WREN instruction may also be used to allow execution of
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. The WRDI instruction will not
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Write-Status-
Register instruction must be executed immediately after the
execution of the Enable-Write-Status-Register instruction.
This two-step instruction sequence of the EWSR instruc-
©2006 Silicon Storage Technology, Inc.
FIGURE 16: W
FIGURE 17: W
RITE
RITE
E
D
NABLE
ISABLE
(WREN) S
(WRDI) S
SCK
CE#
SCK
CE#
SO
SO
SI
EQUENCE
SI
EQUENCE
MODE 3
MODE 0
MODE 3
MODE 0
HIGH IMPEDANCE
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
MSB
0 1 2 3 4 5 6 7
17
the Write-Status-Register (WRSR) instruction; however,
the Write-Enable-Latch bit in the Status Register will be
cleared upon the rising edge CE# of the WRSR instruction.
CE# must be driven high before the WREN instruction is
executed.
terminate any programming operation in progress. Any pro-
gram operation in progress may continue up to T
executing the WRDI instruction. CE# must be driven high
before the WRDI instruction is executed.
tion followed by the WRSR instruction works like SDP (soft-
ware data protection) command structure which prevents
any accidental alteration of the status register values. CE#
must be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction is
executed.
04
06
1295 WRDI.0
1295 WREN.0
S71295-01-000
Data Sheet
BP
after
1/06