PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 165

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

14.3.1
In edge aligned PWM mode, the period is specified by
the value of OCxRS register. In center aligned PWM
mode, the period of the synchronization source such as
Timer's PRy specifies the period. The period in both
cases can be calculated using Equation 14-1.
EQUATION 14-1:
EQUATION 14-2:
EXAMPLE 14-1:
 2010 Microchip Technology Inc.
1. Find the OCxRS register value for a desired PWM frequency of 52.08 kHz, where F
2.
PWM Period = [Value + 1] x T
Where:
Note 1:
Note 1:
clock rate) and a prescaler setting of 1:1 using Edge-Aligned PWM mode.
Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:
Note 1: Based on F
T
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s
PWM Period = (OCxRS + 1) • T
19.2 s
OCxRS
PWM Resolution = log
Value = OCxRS in Edge-Aligned PWM mode
and can be PRy in Center-Aligned PWM mode
(If TMRy is the sync source).
CY
PWM PERIOD
Based on T
and PLL are disabled.
Based on T
= 2 * T
OSC
Maximum PWM Resolution (bits) =
= (OCxRS + 1) • 62.5 ns • 1
= 306
CALCULATING THE PWM
PERIOD
CALCULATION FOR MAXIMUM PWM RESOLUTION
PWM PERIOD AND DUTY CYCLE CALCULATIONS
CY
= 62.5 ns
CY
= (log
= 8.3 bits
= T
= 2 * T
CY
CY
OSC
10
= F
(1)
x (Prescaler Value)
10
OSC
(F
* 2; Doze mode
(16 MHz/52.08 kHz)/log
OSC
CY
; Doze mode and PLL are disabled.
/F
/2; Doze mode and PLL are disabled.
CY
PWM
• (OCx Prescale Value)
)/log
10
PIC24FJ64GB004 FAMILY
Preliminary
2) bits
log
10
10
2) bits
(
F
14.3.2
The PWM duty cycle is specified by writing to the
OCxRS and OCxR registers. The OCxRS and OCxR
registers can be written to at any time, but the duty
cycle value is not latched until a period is complete.
This provides a double buffer for the PWM duty cycle
and is essential for glitchless PWM operation.
Some important boundary parameters of the PWM duty
cycle include:
• Edge-Aligned PWM
• Center-Aligned PWM (with TMRy as the sync
See Example 14-1 for PWM mode timing details.
Table 14-1 and Table 14-2 show example PWM
frequencies and resolutions for a device operating at
4 MIPS and 10 MIPS, respectively.
PWM
- If OCxR and OCxRS are loaded with 0000h,
- If OCxRS is greater than OCxR, the pin will
source)
- If OCxR, OCxRS and PRy are all loaded with
- If OCxRS is greater than PRy, the pin will go
the OCx pin will remain low (0% duty cycle).
remain high (100% duty cycle).
0000h, the OCx pin will remain low (0% duty
cycle).
high (100% duty cycle).
• (Prescale Value)
log
10
F
(2)
PWM DUTY CYCLE
CY
OSC
(1)
(1)
= 8 MHz with PLL (32 MHz device
)
bits
DS39940D-page 165