PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 229

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.7.3
REGISTER 18-21: U1EPn: USB ENDPOINT CONTROL REGISTERS (n = 0 TO 15)
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
LSPD
R/W-0
U-0
—
(1)
These bits are available only for U1EP0, and only in Host mode. For all other U1EPn registers, these bits
are always unimplemented and read as ‘0’.
USB ENDPOINT MANAGEMENT REGISTERS
RETRYDIS
Unimplemented: Read as ‘0’
LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)
1 = Direct connection to a low-speed device is enabled
0 = Direct connection to a low-speed device is disabled
RETRYDIS: Retry Disable bit (U1EP0 only)
1 = Retry NAK transactions are disabled
0 = Retry NAK transactions are enabled; retry done in hardware
Unimplemented: Read as ‘0’
EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN and EPRXEN = 1:
1 = Disable Endpoint n from Control transfers; only Tx and Rx transfers are allowed
0 = Enable Endpoint n for Control (SETUP) transfers; Tx and Rx transfers also are allowed.
For all other combinations of EPTXEN and EPRXEN:
This bit is ignored.
EPRXEN: Endpoint Receive Enable bit
1 = Endpoint n receive is enabled
0 = Endpoint n receive is disabled
EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint n transmit is enabled
0 = Endpoint n transmit is disabled
EPSTALL: Endpoint Stall Status bit
1 = Endpoint n was stalled
0 = Endpoint n was not stalled
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake is enabled
0 = Endpoint handshake is disabled (typically used for isochronous endpoints)
R/W-0
U-0
—
(1)
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
EPCONDIS
R/W-0
U-0
PIC24FJ64GB004 FAMILY
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EPRXEN
R/W-0
U-0
—
EPTXEN
(1)
R/W-0
U-0
—
x = Bit is unknown
EPSTALL
R/W-0
U-0
—
DS39940D-page 229
EPHSHK
R/W-0
U-0
—
bit 8
bit 0