SAF-C505CA-LM Infineon Technologies, SAF-C505CA-LM Datasheet - Page 13

• Manufacturer Part Number: SAF-C505CA-LM
• Description: IC, 8BIT MCU ROM/ROMLESS, SMD
• Manufacturer: Infineon Technologies

Specifications of SAF-C505CA-LM

• No. Of I/o's: 34
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: MQFP
• Supply Voltage: RoHS Compliant
• Core Size: 8bit
• Oscillator Type: External, Internal
• Controller Family/series: C500
• Peripherals: ADC
• Rohs Compliant: Yes

Table 2
Pin Definitions and Functions (cont’d)
Symbol
P2.0-P2.7
PSEN
ALE
*) I = Input
Data Sheet
O = Output
18-25
26
27
Pin Number
I/O
*)
I/O
O
O
Function
Port 2
is a an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1’s written to them are pulled
high by the internal pullup resistors, and in that state can be
used as inputs. As inputs, port 2 pins being externally pulled
low will source current (I
because of the internal pullup resistors. Port 2 emits the
high-order address byte during fetches from external
program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). In this
application it uses strong internal pullup transistors when
issuing 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 issues the
contents of the P2 special function register and uses only
the internal pullup resistors.
The Program Store Enable
output is a control signal that enables the external program
memory to the bus during external fetch operations. It is
activated every three oscillator periods except during
external data memory accesses. Remains high during
internal program execution. This pin should not be driven
during reset operation.
The Address Latch Enable
output is used for latching the low-byte of the address into
external memory during normal operation. It is activated
every three oscillator periods except during an external data
memory access. When instructions are executed from
internal ROM or OTP (EA=1) the ALE generation can be
disabled by bit EALE in SFR SYSCON.
ALE should not be driven during reset operation.
9
C505/C505C/C505A/C505CA
IL
, in the DC characteristics)
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