AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 33

• Manufacturer Part Number: AU80610004671AAS LBMH
• Description: MPU, ATOM PROCESSOR, D410, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D400r

Specifications of AU80610004671AAS LBMH

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.5.4
Datasheet
PCISTS - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
interface. Since the CPU Uncore Device 0 does not physically reside on PCI_A many of
the bits are not implemented.
This status register reports the occurrence of error events on Device 0's PCI
Bit
Bit
15
14
13
12
11
0
Access
Access
RWC
RWC
RWC
RWC
RO
RO
Default
Default
Value
Value
0b
0b
0b
0b
0b
0b
RST/
RST/
PWR
PWR
Core
Core
Core
Core
Core
Core
0/0/0/PCI
6-7h
0090h
16 bits
RWC; RO;
I/O Access Enable (IOAE):
Uncore and is hardwired to a 0. Writes to
this bit position have no effect.
Detected Parity Error (DPE):
This bit is set when this Device receives a
Poisoned TLP.
Signaled System Error (SSE):
0 generates an SERR message over DMI for any
enabled Device 0 error condition. Device 0 error
conditions are enabled in the PCICMD,
ERRCMD, and DMIUEMSK registers. Device 0
error flags are read/reset from the PCISTS,
ERRSTS, or DMIUEST registers. Software clears
this bit by writing a 1 to it.
Received Master Abort Status (RMAS):
a DMI request that receives an Unsupported
Request completion packet. Software clears this
bit by writing a 1 to it.
Received Target Abort Status (RTAS):
a DMI request that receives a Completer Abort
completion packet. Software clears this bit by
writing a 1 to it.
Signaled Target Abort Status (STAS):
Abort DMI completion packet or Special Cycle.
This bit is not implemented in the CPU Uncore
and is hardwired to a 0. Writes to this bit
position have no effect.
This bit is not implemented in the CPU
This bit is set to 1 when the CPU Uncore Device
This bit is set when the CPU Uncore generates
This bit is set when the CPU Uncore generates
The CPU Uncore will not generate a Target
Description
Description
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