MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 8

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Modules List
3
The i.MX53xD processor contains a variety of digital and analog modules.
modules in alphabetical order.
8
Mnemonic
AUDMUX
ECSPI-1
ECSPI-2
CAMP-1
CAMP-2
Block
ASRC
CCM
CSPI
ARM
GPC
SRC
CSU
Modules List
ARM Platform
Asynchronous
Sample Rate
Converter
Digital Audio
Multiplexer
Clock Amplifier
Clock Control
Module
Global Power
Controller
System Reset
Controller
Configurable
SPI, Enhanced
CSPI
Central Security
Unit
Block Name
i.MX53xD Applications Processors for Consumer Products, Rev. 3
ARM
Multimedia
Peripherals
Multimedia
Peripherals
Clocks,
Resets, and
Power Control
Clocks,
Resets, and
Power Control
Connectivity
Peripherals
Security
Subsystem
Table 2. i.MX53xD Digital and Analog Blocks
The ARM Cortex A8
r2p5 (with TrustZone) and its essential sub-blocks. It contains the 32 Kbyte
L1 instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and
a 256 Kbyte L2 cache. The platform also contains an event monitor and
debug modules. It also has a NEON coprocessor with SIMD media
processing architecture, a register file with 32/64-bit general-purpose
registers, an integer execute pipeline (ALU, Shift, MAC), dual
single-precision floating point execute pipelines (FADD, FMUL), a
load/store and permute pipeline and a non-pipelined vector floating point
(VFP Lite) coprocessor supporting VFPv3.
The asynchronous sample rate converter (ASRC) converts the sampling
rate of a signal associated to an input clock into a signal associated to a
different output clock. The ASRC supports concurrent sample rate
conversion of up to 10 channels of about –120 dB THD+N. The sample rate
conversion of each channel is associated to a pair of incoming and outgoing
sampling rates. The ASRC supports up to three sampling rate pairs.
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example,
SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice
codecs). The AUDMUX has seven ports (three internal and four external)
with identical functionality and programming models. A desired connectivity
is achieved by configuring two or more AUDMUX ports.
Clock amplifier
These modules are responsible for clock and reset distribution in the
system, as well as for system power management.
The system includes four PLLs.
Full-duplex enhanced synchronous serial interface, with data rates
16-60 Mbit/s. It is configurable to support master/slave modes. In Master
mode it supports four slave selects for multiple peripherals.
The central security unit (CSU) is responsible for setting comprehensive
security policy within the i.MX53xD platform, and for sharing security
information between the various security modules. The security control
registers (SCR) of the CSU are set during boot time by the high assurance
boot (HAB) code and are locked to prevent further writing.
TM
Platform consists of the ARM processor version
Brief Description
Table 2
describes these
Freescale Semiconductor