MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 91

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.7.8.6
4.7.8.6.1
The IPU uses four control signals and data to operate a standard synchronous interface:
All synchronous display controls are generated on the base of an internally generated “local start point”.
The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.
The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved
relative to the local start point. The data bus of the synchronous interface is output direction only.
4.7.8.6.2
Figure 47
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
Freescale Semiconductor
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VSYNC
HSYNC
IPP_DISP_CLK
HSYNC
DRDY
IPP_DISP_CLK—Clock to display
HSYNC—Horizontal synchronization
VSYNC—Vertical synchronization
DRDY—Active data
DI_CLK internal DI clock, used for calculation of other controls.
IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, IPP_DISP_CLK runs continuously.
HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.)
VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPP_PIN_3 is used as VSYNC.)
DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
IPP_DATA
depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure
Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
IPU Display Operating Signals
LCD Interface Functional Description
Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels
i.MX53xD Applications Processors for Consumer Products, Rev. 3
LINE 1
1
LINE 2
2
LINE 3
3
LINE 4
LINE n-1
m–1
Electrical Characteristics
LINE n
m
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