P89LPC9103FTK NXP Semiconductors, P89LPC9103FTK Datasheet
P89LPC9103FTK
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P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core byte-erasable flash with 8-bit A/D converter Rev. 03 — 10 July 2007 1. General description The P89LPC9102/9103/9107 are single-chip microcontrollers in low-cost 10-pin and 14-pin packages based on ...
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... NXP Semiconductors I In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage. I Serial flash ICP allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. I Watchdog timer with separate on-chip oscillator, requiring no external components. ...
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... P89LPC9102FTK HVSON10 P89LPC9103FTK P89LPC9107FDH TSSOP14 P89LPC9107FN DIP14 4.1 Ordering options Table 3. Type number P89LPC9102FTK P89LPC9103FTK P89LPC9107FDH P89LPC9107FN P89LPC9102_9103_9107_3 Product data sheet P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core Description plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 3 0.85 mm plastic thin shrink small outline package ...
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... NXP Semiconductors 5. Block diagram P89LPC9102 P1.2, P1.5 P0[1:5], P0.7 KBI1 KBI2 CLKOUT CLKIN Fig 1. Block diagram of P89LPC9102 P89LPC9102_9103_9107_3 Product data sheet 8-bit microcontrollers with two-clock accelerated 80C51 core ACCELERATED 2-CLOCK 80C51 CPU 1 kB FLASH internal bus PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os ...
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... NXP Semiconductors P1.0, P1.1, P1.5 P0[1:5] KBI1 KBI2 CLKIN Fig 2. Block diagram of P89LPC9103 P89LPC9102_9103_9107_3 Product data sheet 8-bit microcontrollers with two-clock accelerated 80C51 core P89LPC9103 ACCELERATED 2-CLOCK 80C51 CPU 1 kB FLASH internal bus PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os KEYPAD INTERRUPT ...
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... NXP Semiconductors P1[0:2], P1.5 P0[1:5], P0.7 KBI1 KBI2 CLKOUT CLKIN Fig 3. Block diagram of P89LPC9107 6. Functional diagram DAC1 Fig 4. Functional diagram of P89LPC9102 P89LPC9102_9103_9107_3 Product data sheet 8-bit microcontrollers with two-clock accelerated 80C51 core P89LPC9107 ACCELERATED 2-CLOCK 80C51 CPU 1 kB FLASH internal bus ...
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... NXP Semiconductors DAC1 Fig 5. Functional diagram of P89LPC9103 DAC1 Fig 6. Functional diagram of P89LPC9107 P89LPC9102_9103_9107_3 Product data sheet P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core AD13 CIN1A CMPREF CLKIN PORT 0 AD11 KBI2 CIN1B AD12 KBI1 AD10 AD13 CIN1A CLKIN CMPREF KBI2 AD11 ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 7. P89LPC9102 pinning (HVSON10) Fig 8. P89LPC9103 pinning (HVSON10) Fig 9. P89LPC9107 pinning (TSSOP14) P89LPC9102_9103_9107_3 Product data sheet P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core terminal 1 index area 1 P0.2/KBI2/AD11 P1.5/RST 2 LPC9102 P0.1/KBI1/AD10 4 P1.2/T0 5 002aaa969 Transparent top view ...
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... NXP Semiconductors Fig 10. P89LPC9107 pinning (DIP14) P89LPC9102_9103_9107_3 Product data sheet P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core P0.2/KBI2/AD11 1 14 P0.3/CIN1B/AD12 2 13 n.c. n.c. P1.5/RST 3 12 P0.4/CIN1A/AD13/DAC1 LPC9107 P0.5/CMPREF/CLKIN P0.1/KBI1/AD10 V P1.0/TXD 6 9 P1.1/RXD 7 P1.2/T0 8 P0.7/T1/CLKOUT 002aac987 Rev. 03 — 10 July 2007 DD © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors 7.2 Pin description Table 4. P89LPC9102 pin description Symbol Pin Type P0.1 to P0.5, I/O P0.7 P0.1/KBI1/ 4 I/O AD10 I I P0.2/KBI2/ 1 I/O AD11 I I P0.3/CIN1B/ 10 I/O AD12 I I P0.4/CIN1A/ 9 I/O AD13/DAC1 P0.5/CMPRE 8 I/O F/CLKIN I I P0.7/T1/ 6 I/O CLKOUT I/O I P1.2, P1.5 I/O P1 ...
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... NXP Semiconductors Table 4. P89LPC9102 pin description Symbol Pin Type P1.5/RST P89LPC9102_9103_9107_3 Product data sheet P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core …continued Description P1.5 — Port 1 bit 5 (input-only). RST — External Reset input during power- selected via User Configuration Register 1 (UCFG1) ...
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... NXP Semiconductors Table 5. P89LPC9103 pin description Symbol Pin Type P0.1 to P0.5 I/O P0.1/KBI1/ 4 I/O AD10 I I P0.2/KBI2/ 1 I/O AD11 I I P0.3/CIN1B/ 10 I/O AD12 I I P0.4/CIN1A/ 9 I/O AD13/DAC1 P0.5/CMPREF/ 6 I/O CLKIN I I P1.0 to P1.5 I/O P1.0/TXD 5 I/O O P1.1/RXD 6 I/O I P89LPC9102_9103_9107_3 Product data sheet ...
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... NXP Semiconductors Table 5. P89LPC9103 pin description Symbol Pin Type P1.5/RST Table 6. P89LPC9107 pin description Symbol Pin Type P0.1 to P0.5, I/O P0.7 P0.1/KBI1/ 5 I/O AD10 I I P0.2/KBI2/ 1 I/O AD11 I I P0.3/CIN1B/ 14 I/O AD12 I I P0.4/CIN1A/ 12 I/O AD13/DAC1 P0.5/CMPREF/ 11 I/O CLKIN I I P0.7/T1/ ...
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... NXP Semiconductors Table 6. P89LPC9107 pin description Symbol Pin Type P1.0 to P1.2, I/O P1.5 P1.0/TXD 6 I/O O P1.1/RXD 9 I/O I P1.2/T0 7 I/O I/O P1.5/RST P89LPC9102_9103_9107_3 Product data sheet P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core …continued Description Port 1: Port I/O port with a user-configurable output type. During reset Port 1 latches are confi ...
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... NXP Semiconductors 8. Functional description Remark: Please refer to the P89LPC9102/9103/9107 User manual UM10112 for a more detailed functional description. 8.1 Special function registers Remark: Special Function Registers (SFRs) accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. ...
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Table 7. P89LPC9102 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H ADCON1 A/D control register 1 97H ADINS A/D input select A3H ADMODA A/D mode register A C0H ADMODB ...
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Table 7. P89LPC9102 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address IEN1* Interrupt enable 1 E8H Bit address IP0* Interrupt priority 0 B8H IP0H Interrupt priority 0 high B7H Bit address IP1* ...
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Table 7. P89LPC9102 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. RSTSRC Reset source register DFH RTCCON Real-time clock control D1H RTCH Real-time clock register high D2H RTCL Real-time clock register low D3H SP ...
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Table 8. P89LPC9103 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H ADCON1 A/D control register 1 97H ADINS A/D input select A3H ADMODA A/D mode register A C0H ADMODB ...
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Table 8. P89LPC9103 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. FMDATA Program flash data E5H IEN0* Interrupt enable 0 A8H Bit address IEN1* Interrupt enable 1 E8H Bit address IP0* Interrupt priority 0 ...
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Table 8. P89LPC9103 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address PSW* Program status word D0H PT0AD Port 0 digital input disable F6H RSTSRC Reset source register DFH RTCCON Real-time clock control ...
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All ports are in input-only (high-impedance) state after power-up. [4] The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is ...
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Table 9. P89LPC9107 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H ADCON1 A/D control register 1 97H ADINS A/D input select A3H ADMODA A/D mode register A C0H ADMODB ...
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Table 9. P89LPC9107 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. FMDATA Program flash data E5H IEN0* Interrupt enable 0 A8H Bit address IEN1* Interrupt enable 1 E8H Bit address IP0* Interrupt priority 0 ...
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Table 9. P89LPC9107 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address PSW* Program status word D0H PT0AD Port 0 digital input disable F6H RSTSRC Reset source register DFH RTCCON Real-time clock control ...
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Table 9. P89LPC9107 special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address TCON* Timer 0 and 1 control 88H TH0 Timer 0 high 8CH TH1 Timer 1 high 8DH TL0 Timer 0 low ...
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... NXP Semiconductors 8.2 Enhanced CPU The P89LPC9102/9103/9107 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 8.3 Clocks 8.3.1 Clock definitions The P89LPC9102/9103/9107 device has internal clocks as defined below: OSCCLK — ...
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... NXP Semiconductors 8.5 Watchdog oscillator option The watchdog timer has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed. Fig 11. Block diagram of P89LPC9102 oscillator control Fig 12. Block diagram of P89LPC9103/9107 oscillator control 8.6 External clock input option In this confi ...
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... NXP Semiconductors frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V specified operating voltage. 8.7 CCLK wake-up delay The P89LPC9102/9103/9107 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. ...
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... NXP Semiconductors Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source ...
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... NXP Semiconductors RTCF ERTC (RTCCON.1) WDOVF ENADCI1 ADCI1 ENBI1 BNDI1 EAD Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9103/9107) 8.12 I/O ports The P89LPC9102/9103/9107 has either I/O pins depending on the reset pin option and clock source option chosen. Refer to Table 10 ...
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... NXP Semiconductors 8.12.2 Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW driven strongly and able to sink a fairly large current ...
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... NXP Semiconductors • After power-up all I/O pins, except P1.5, may be configured by software. • Pin P1.5 is input-only. Every output on the P89LPC9102/9103/9107 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded ...
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... NXP Semiconductors 8.14.2 Slow-down mode using the DIVM register Slow-down mode is achieved by dividing down the OSCCLK frequency to generate CCLK. This division is accomplished by configuring the DIVM register to divide OSCCLK 510 times. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption ...
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... NXP Semiconductors • Power-on detect • Brownout detect • Watchdog timer • Software reset • UART break character detect reset (P89LPC9103/9107). For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one fl ...
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... NXP Semiconductors 8.16.6 Timer overflow toggle output (P89LPC9102/9107) Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overfl ...
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... NXP Semiconductors 8.18.4 Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9 the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in section Section 8.18.5 “ ...
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... NXP Semiconductors 8.18.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated when the double buffer is ready to receive new data. th 8.18.10 The 9 If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out ...
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... NXP Semiconductors 8.21 Comparator interrupt The comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. 8.22 Comparator and power reduction modes The comparator may remain enabled when Power-down mode or Idle mode is activated, but the comparator is disabled automatically in Total Power-down mode ...
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... NXP Semiconductors taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog timer feature is disabled, it can be used as an interval timer and may generate an interrupt. ...
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... NXP Semiconductors 8.26 Flash program memory 8.26.1 General description The P89LPC9102/9103/9107 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory ...
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... NXP Semiconductors 8.26.5 In-circuit programming In-Circuit Programming is performed without removing the microcontroller from the system. The In-Circuit Programming facility consists of internal hardware resources to facilitate remote programming of the P89LPC9102/9103/9107 through a two-wire serial interface. The NXP In-Circuit Programming facility has made in-circuit programming in an embedded application, using commercially available programmers, possible with a minimum of additional expense in components and circuit board area ...
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... NXP Semiconductors 9. A/D Converter 9.1 General description The P89LPC9102/9103/9107 has an 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter. The A/D consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the Successive Approximation Register (SAR) drives a digital-to-analog converter which provides the other input to the comparator ...
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... NXP Semiconductors 9.3 Block diagram Fig 18. ADC block diagram 9.4 A/D operating modes 9.4.1 Fixed channel, single conversion mode A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel ...
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... NXP Semiconductors 9.4.5 Dual channel, continuous conversion mode This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in result register, AD1DAT0. The result of the conversion of the second channel is placed in result register, AD1DAT1. The fi ...
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... NXP Semiconductors 9.9 Power-down and Idle mode In Idle mode the A/D converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power ...
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... NXP Semiconductors 10. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T bias ambient temperature amb(bias) T storage temperature stg I HIGH-level output current per OH(I/O) input/output pin I LOW-level output current per OL(I/O) input/output pin I maximum total input/output current ...
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... NXP Semiconductors 11. Static characteristics Table 12. Static characteristics 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current I total Power-down mode ...
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... NXP Semiconductors Table 12. Static characteristics 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V brownout trip voltage bo V band gap reference voltage ref(bg) TC band gap temperature bg coefficient [1] Typical ratings are not guaranteed. The values listed are at room temperature ...
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... NXP Semiconductors 12. Dynamic characteristics Table 13. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency T clock cycle time cy(clk) f low-power select clock CLKLP ...
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... NXP Semiconductors Table 14. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator osc(RC) frequency f internal watchdog osc(WD) oscillator frequency T clock cycle time cy(clk) f low-power select clock CLKLP frequency External clock ...
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... NXP Semiconductors 12.1 Waveforms clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 19. Shift register mode timing (P89LPC9103/9107 0.2V 0.2V 0.45 V Fig 20. External clock timing P89LPC9102_9103_9107_3 Product data sheet 8-bit microcontrollers with two-clock accelerated 80C51 core T XLXL t XHQX ...
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... NXP Semiconductors 13. Other characteristics 13.1 Comparator electrical characteristics Table 15. Comparator electrical characteristics 3.6 V, unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V input offset voltage IO V common-mode input voltage IC CMRR common-mode rejection ratio t total response time ...
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... NXP Semiconductors 14. Package outline HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 0. terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors 15. Abbreviations Table 17. Acronym A/D BOE CMRR DAC EMI IAP ICP LSB MSB PWM RTC SAR UART P89LPC9102_9103_9107_3 Product data sheet P89LPC9102/9103/9107 8-bit microcontrollers with two-clock accelerated 80C51 core Acronym list Description Analog-to-Digital Brownout Enable Common-Mode Rejection Ratio Digital-to-Analog Converter ...
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... Data sheet status 20070710 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added new device P89LPC9107FN. ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 Product comparison overview . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Functional description . . . . . . . . . . . . . . . . . . 15 8.1 Special function registers ...
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... NXP Semiconductors 9.4.5 Dual channel, continuous conversion mode . . 45 9.4.6 Single step mode . . . . . . . . . . . . . . . . . . . . . . 45 9.5 Conversion start modes . . . . . . . . . . . . . . . . . 45 9.5.1 Timer triggered start . . . . . . . . . . . . . . . . . . . . 45 9.5.2 Start immediately . . . . . . . . . . . . . . . . . . . . . . 45 9.6 Boundary limits interrupt 9.7 DAC output to a port pin with high output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.8 Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.9 Power-down and Idle mode ...