P89V51RC2FN NXP Semiconductors, P89V51RC2FN Datasheet - Page 31

• Manufacturer Part Number: P89V51RC2FN
• Description: IC, MCU 8BIT 80C51 32K FLASH, DIP40
• Manufacturer: NXP Semiconductors

Specifications of P89V51RC2FN

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 32
• Program Memory Size: 32KB
• Ram Memory Size: 1KB
• Cpu Speed: 33MHz
• Oscillator Type: External Only
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Package: 40PDIP
• Device Core: 80C51
• Family Name: 89V
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
6.5 Timer 2
Timer 2 is a 16-bit Timer/counter which can operate as either an event timer or an event
counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four
operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate
Generator which are selected according to
Table
Table 19.
Table 20.
Bit addressable; Reset value: 00H
Table 21.
RCLK + TCLK
0
0
0
1
X
Bit
7
6
5
Bit
Symbol
Fig 11. Timer/counter 0 mode 3 (two 8-bit counters)
21) and T2MOD
INT0 pin
TnGate
T0 pin
osc/6
TR0
Timer 2 operating mode
T2CON - Timer/counter 2 control register (address C8H) bit allocation
T2CON - Timer/counter 2 control register (address C8H) bit description
Symbol
TF2
EXF2
RCLK
TF2
7
CP/RL2
0
1
0
X
X
Rev. 05 — 12 November 2009
(Table 22
EXF2
6
osc/2
Description
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by
software. TF2 will not be set when either RCLK or TCLK = 1 or when
Timer 2 is in Clock-out mode.
Timer 2 external flag is set when Timer 2 is in capture, reload or
baud-rate mode, EXEN2 = 1 and a negative transition on T2EX
occurs. If Timer 2 interrupt is enabled EXF2 = 1 causes the CPU to
vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software.
Receive clock flag. When set, causes the UART to use Timer 2
overflow pulses for its receive clock in modes 1 and 3. RCLK = 0
causes Timer 1 overflow to be used for the receive clock.
TR1
C/T = 0
C/T = 1
TR2
1
1
1
1
0
RCLK
and
5
Table
TCLK
Table 19
23).
P89V51RB2/RC2/RD2
control
control
4
T2OE
0
0
1
0
X
8-bit microcontrollers with 80C51 core
EXEN2
using T2CON
(8-bits)
(8-bits)
TH0
TL0
3
overflow
overflow
Mode
16-bit auto reload
16-bit capture
programmable clock-out
baud rate generator
off
TR2
2
(Table 20
TF0
TF1
© NXP B.V. 2009. All rights reserved.
C/T2
1
002aaa522
and
interrupt
interrupt
CP/RL2
31 of 80
0