SST39VF1681-70-4C-EKE SILICON STORAGE TECHNOLOGY, SST39VF1681-70-4C-EKE Datasheet - Page 2

• Manufacturer Part Number: SST39VF1681-70-4C-EKE
• Description: IC, 16M FLASH MEMORY, 2KWORD SECTOR
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST39VF1681-70-4C-EKE

• Memory Size: 16Mbit
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Access Time: 70ns
• Interface: X8 MPF+
• Memory Configuration: 2M X 8bit
• Memory Type: Flash - NOR
• Interface Type: CFI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Preliminary Specifications
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39VF168x also have the Auto Low Power mode
which puts the device in a near standby mode after data
has been accessed with a valid Read operation. This
reduces the I
typically 3 µA. The Auto Low Power mode reduces the typi-
cal I
Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF168x is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output con-
trol and is used to gate data from the output pins. The
data bus is in high impedance state when either CE# or
OE# is high. Refer to the Read cycle timing diagram for
further details (Figure 3).
Byte-Program Operation
The SST39VF168x are programmed on a byte-by-byte
basis. Before programming, the sector where the byte
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load byte address and byte data. During the Byte-
Program operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Pro-
gram operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Program
operation, once initiated, will be completed within 10 µs.
See Figures 4 and 5 for WE# and CE# controlled Program
operation timing diagrams and Figure 19 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
©2003 Silicon Storage Technology, Inc.
DD
active read current to the range of 2 mA/MHz of
DD
active read current from typically 9 mA to
2
commands issued during the internal Program operation
are ignored. During the command sequence, WP# should
be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF168x offer both Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 4 KByte. The Block-Erase mode
is based on uniform block size of 64 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (50H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms and Figure 23 for the flowchart. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored. When WP# is low, any attempt to Sector-
(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ
mode, a Byte-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
2
toggling and DQ
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
6
at “1”. While in Erase-Suspend
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