STA333W STMicroelectronics, STA333W Datasheet
STA333W
Specifications of STA333W
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STA333W Summary of contents
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... AM radio interference reduction modes. The serial audio data input interface accepts all possible formats, including the popular I channels of DDX The STA333W is part of the Sound Terminal™ family that provides full digital audio streaming to the speaker offering cost effectiveness, low power input mode support dissipation and sound enrichment ...
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... Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.1 5.3.2 5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/49 Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 13365 Rev 2 STA333W ...
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... STA333W 5.4.1 5.4.2 5.4.3 5.4.4 6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 Configuration registers (addr 0x00 to 0x05 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 Volume control registers (addr 0x06 to 0x09 6.2.1 6.2.2 6.2.3 6.3 Automodes™ register (0x0C 6.4 Channel configuration registers (addr 0x0E, 0x0F ...
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... Contents 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 47 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4/49 Doc ID 13365 Rev 2 STA333W ...
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... STA333W List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Thermal data Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Electrical characteristics for digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Electrical specifications for power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Register summary Table 9. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 10. ...
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... THD vs. frequency (V Figure 18. FFT 0 dBfs (V CC Figure 19. FFT -60 dBfs (V CC Figure 20. THD vs. frequency (V Figure 21. Double-layer PCB with two copper ground areas and 16 vias . . . . . . . . . . . . . . . . . . . . . . 44 Figure 22. Power derating curve for PCB used as heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 23. PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6/ Doc ID 13365 Rev 2 STA333W ...
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... STA333W 1 Block diagram Figure 1. Block diagram interface Volume control PLL Digital DSP Protection current/thermal Power control DDX Regulators Doc ID 13365 Rev 2 Block diagram Channel 1A Channel 1B Logic Channel 2A Channel 2B Bias Power 7/49 ...
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... Output half bridge 2B GND2 Power negative supply VCC2 Power positive supply OUT2A Output half bridge 2A Doc ID 13365 Rev 2 36 VDD_DIG 35 GND_DIG 34 SCL 33 SDA 32 INT_LINE 31 RESET 30 SDI 29 LRCKI 28 BICKI 27 XTI 26 GND_PLL FILTER_PLL 25 VDD_PLL 24 PWRDN 23 GND_DIG 22 VDD_DIG 21 20 N.C. 19 N.C. D05AU1638 Description - 3 reference STA333W ...
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... STA333W Table 2. Pin description (continued) Number Type PWR 12 PWR PWR 15 PWR PWR 22 PWR PWR PWR I PWR 36 PWR - - Name OUT1B Output half bridge 1B VCC1 Power positive supply GND1 Power negative supply OUT1A Output half bridge 1A GND_REG Internal ground reference VDD_REG Internal 3.3-V reference voltage ...
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... Thermal data Table 3. Thermal data Symbol R Thermal resistance junction to case (thermal pad) Th(j-case) T Thermal-shutdown junction temperature sd T Thermal-warning temperature w T Thermal-shutdown hysteresis hsd 10/49 Parameter Doc ID 13365 Rev 2 STA333W Min Typ Max Unit - 1.5 2.0 °C/W 140 150 160 °C - 130 - ° ° ...
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... STA333W 3 Electrical specification 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol V Analog supply voltage (pins VCCx Digital supply voltage (pins VDD_DIG Logic input interface L T Operating junction temperature op T Storage temperature stg Warning: 3.2 Recommended operating conditions Table 5. Recommended operating conditions ...
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... R L Parameter Conditions THD = 1% THD = 10 dsON dsON Resistive load, refer to Figure 5 Refer to Figure 6 Resistive load, refer to Figure 5 Resistive load, refer to Figure 5 Doc ID 13365 Rev 2 STA333W Min Typ Max Unit - - ±10 µ ±10 µ ...
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... STA333W Table 7. Electrical specifications for power section (continued) Symbol V Supply voltage CC Supply current from V power down I VCC Supply current from V operation Supply current for DDX processing (reference only) I VDD_DIG Supply current in standby I Overcurrent limit LIM I Short-circuit protection SCP Undervoltage protection V UVP ...
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... C program sequence start specific VCC and VDD_DIG turn-off sequence is required FE FE Don’t care Don’t care Doc ID 13365 Rev 2 STA333W below ensure a pop-free turn TC TC Don’t care Don’t care Don’t care Don’t care Don’t care Don’ ...
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... STA333W 3.6 Testing Figure 5. Test circuit Duty cycle = 50% Figure 6. Current dead-time test circuit Duty cycle=A DTin(A) INA Low current dead time = MAX(DTr,DTf) +Vcc M58 OUTxY INxY M57 gnd High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B DTout(A) M58 Q1 Rload=8Ω ...
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... Functional description 4.1 Functional pins 4.1.1 Power-down function Pin PWRDN (23) is used to power down the STA333W. PWRDN = 0 (0 V): power-down state. PWRND = During the power-down sequence the output begins to mute. After the mute condition is reached the power stage is switched off and the output becomes high impedance. Then the master clock to all internal hardware blocks is gated off ...
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... Serial audio interface protocols The STA333W serial audio input was designed to interface with standard digital audio components and to accept serial data formats. The STA333W always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28), and serial data SDI (pin 30) ...
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... The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode and 0 for write mode. After a START condition the STA333W identifies the device address on the SDA bus and if a match is found, acknowledges the identification during the 9th bit time. The byte following the device identification byte is the internal space address ...
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... After receiving, the internal byte address the STA333W again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA333W acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition ...
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... Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333W. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer. Figure 10. Read-mode sequence ...
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... STA333W 6 Register description Table 8. Register summary Addr Name 0x00 CONFA 0x01 CONFB 0x02 CONFC 0x03 CONFD 0x04 CONFE 0x05 CONFF 0x06 MUTE 0x07 MVOL 0x08 C1VOL 0x09 C2VOL 0x0C AUTO 0x0E C1CFG 0x0F C2CFG 0x27 MPCC1 0x28 MPCC2 0x29 DCC1 0x2A ...
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... R/W 2 R/W The STA333W supports sample rates of 32 kHz, 44.1 kHz, 48 KHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: 32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz ...
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... R/W 4:3 R/W The STA333W has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits. ...
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... R/W 6 R/W The on-chip STA333W power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block will force a -3dB output limit (determined by TWOCL in coefficient RAM) to the modulation limit in an attempt to eliminate the thermal warning condition ...
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... Serial data interface The STA333W audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA333W always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data SDI. ...
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... Left justified 18-bit data 1101 1 Left justified 16-bit data 0010 1 Right justified 24-bit data 0110 1 Right justified 20-bit data 1010 1 Right justified 18-bit data 1110 1 Right justified 16-bit data Doc ID 13365 Rev 2 STA333W Interface format 2 S 16-bit data 2 S 16-bit data ...
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... STA333W Channel input mapping Table 20. Channel input mapping Bit R/W 6 R/W 7 R/W Each channel received via I channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I 6.1.3 Configuration register C (addr 0x02 OCRB Reserved 1 0 DDX power output mode Table 21 ...
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... ZDE 1: enable the automatic zero-detect mute D5 D4 DCCV PWMS 0 0 RST Name 0: use standard MPC coefficient 0 MPCV 1: use MPCC bits for MPC coefficient Doc ID 13365 Rev 2 Description (Output limit register (addr Reserved Description AME NSBW MPC Description STA333W then S D0 MPCV 0 ...
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... R/W 1 R/W Setting the MPC bit turns on special processing that corrects the STA333W power device at high power. This mode lowers the THD full DDX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1:0] = 01) and binary. When OCFG = 00, MPC does not affect channels 3 and 4, the line-out channels ...
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... D5 D4 ECLE LDTE RST Name 1 IDE 1: enables the automatic invalid input detect mute RST Name 1 BCLE Binary output mode clock loss detection enable Doc ID 13365 Rev 2 Description Description BCLE IDE Reserved Description 2 S data and will Description STA333W D0 0 ...
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... STA333W LRCK double trigger protection Table 35. LRCK double trigger protection Bit R/W 4 R/W Actively prevents double trigger of LRCLK. Auto EAPD on clock loss Table 36. Auto EAPD on clock loss Bit R/W 5 R/W When active will issue a power device power-down signal (EAPD) on clock loss detection. ...
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... MMUTE 1: all channels are in mute condition RST Name Channel 1 mute: 0 C1M 0: not muted possible to set the channel volume 1: hardware muted Channel 2 mute: 0 C2M 0: not muted possible to set the channel volume 1: hardware muted Doc ID 13365 Rev C2M C1M Description Description STA333W D0 MMUTE 0 ...
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... Volume setting The volume structure of the STA333W consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5-dB steps from + -80 dB example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB ...
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... AMAME 1: switching frequency determined by AMAM setting 48 kHz / 96 kHz input f 0.535 MHz - 0.720 MHz 0.721 MHz - 0.900 MHz Doc ID 13365 Rev 2 Volume AMAM2 AMAM1 AMAM0 Description 44.1 kHz / 88.2 kHz input f S 0.535 MHz - 0.670 MHz 0.671 MHz - 0.800 MHz STA333W D0 AMAME 0 S ...
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... STA333W Table 44. Automodes™ AM switching frequency selection 010 011 100 101 110 6.4 Channel configuration registers (addr 0x0E, 0x0F Volume bypass Each channel contains an individual channel volume bypass particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel ...
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... Thermal fault: - TFAULT 0: junction temperature limit detection 1: normal operation Doc ID 13365 Rev DCC11 DCC10 DCC9 DCC3 DCC2 DCC1 FDRC11 FDRC10 FDRC9 FDRC3 FDRC2 FDRC1 OCWARN TFAULT Description STA333W D0 DCC8 1 D0 DCC0 1 D0 FDRC8 0 D0 FDRC0 0 D0 TWARN ...
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... Postscale The STA333W provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel, which can be used to limit the maximum modulation index and therefore the peak current through the power device. The register values represent an 8-bit signed fractional number. This number is extended to a 24-bit number, by adding zeros to the right, and then directly multiplied by the data on that channel ...
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... OLIM7 OLIM6 0 The STA333W provides a simple mechanism for reacting to a thermal or overcurrent warning in the power device. When the TWARN or OCWARN status bit is asserted, the output is limited to the OLIM setting. The limit can be adjusted by modifying the thermal warning/overcurrent output limit value. As for the normal postscale, the register value represents an 8-bit signed fractional number ...
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... Applications scheme for power supplies Figure 11 below shows a typical applications scheme for STA333W. Special care has to be taken with regard to the power supplies when laying out the PCB. In particular the 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device ...
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... Doc ID 13365 Rev 2 STA333W 100nF 100nF 100nF 470nF 470nF 470nF LEFT LEFT LEFT 100nF 100nF 100nF 100nF 100nF 100nF 470nF ...
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... STA333W 8 Characterization data The following characterizations were made with R stated. Figure 14. Output power vs. supply voltage (THD = 1 Figure 15. FFT 0 dBfs (V +10 + -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 - -70 - -80 - -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 -150 Ω and kHz unless otherwise L 4 Ω ...
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... Figure 17. THD vs. frequency (V 1 0.5 0.2 % 0.1 0.05 0.02 0.01 20 42/ 100 100 200 200 500 500 Ω 6ohm 50 100 200 500 Hz Doc ID 13365 Rev 10k 10k 20k 20k 4 Ω 4ohm 8 Ω 8ohm 10k STA333W 20k ...
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... STA333W Figure 18. FFT 0 dBfs (V +10 + -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 - -70 - -80 - -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 -150 20 20 Figure 19. FFT -60 dBfs (V +10 + -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 - -70 - -80 - -90 -90 -100 -100 -110 -110 -120 ...
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... Given that the amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level the maximum estimated dissipated power for the STA333W With the above suggested board as heatsink, a maximum junction temperature rise, ∆Tj °C is possible. In consumer environments where 50 °C is the maximum ambient ...
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... STA333W 10 Package mechanical data The STA333W comes in a 36-pin PowerSSO package with exposed pad down (EPD). Figure 23 below shows the package outline and Figure 23. PowerSSO-36 EPD outline drawing Table 47 gives the dimensions. Doc ID 13365 Rev 2 Package mechanical data 45/49 ...
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... Dimensions in inches Min Typ 0.085 - 0.097 0.085 - 0.094 0.000 - 0.004 0.007 - 0.014 0.009 - 0.013 0.398 - 0.413 0.291 - 0.299 - 0.020 - - 0.335 - - 0.091 - - - 0.004 0.398 - 0.413 - - 0.016 degrees 0.024 - 0.039 - 0.169 - - - 10 degrees - 0.047 - - 0.031 - - 0.114 - - 0.144 - - 0.039 - 0.161 - 0.185 0.193 - 0.280 STA333W Max ® ...
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... STA333W 11 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. Automodes is a trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. Sound Terminal is a trademark of STMicroelectronics. Trademarks and other acknowledgements Doc ID 13365 Rev 2 47/49 ...
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... Updated package Y (Min) dimension in Removed references to STA50x/51x throughout the document Doc ID 13365 Rev 2 Changes on page 1 on page 1 Table 4, Table 3 and Chapter 5: I Table 8: Register summary on Configuration register D (addr 0x03) on page 28 Table 25 on page 28 Output limit Section 7.3 on page 40 Table 47 on page 46 STA333W Table Device ...
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... STA333W Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...