CS4382-KQ Cirrus Logic Inc, CS4382-KQ Datasheet - Page 16

• Manufacturer Part Number: CS4382-KQ
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4382-KQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.5V
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• No. Of Channels: 8
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.1.5
3.2
3.2.1
16
Reserved
DIF2
DIF2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Function:
Function:
7
0
POWER DOWN (PDN)
Mode Control 2 (address 02h)
DIGITAL INTERFACE FORMAT (DIF)
Default = 1
0 - Disabled
1 - Enabled
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 33-38.
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by the Digital Interface Format pins.
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation in Control Port mode can occur.
DIF1
DIF1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DIF2
6
0
DIFO
DIF0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DIF1
Table 1. Digital Interface Formats - PCM Mode
Table 2. Digital Interface Formats - DSD Mode
5
0
Left Justified, up to 24-bit data
I
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
2
S, up to 24-bit data
DIF0
4
0
DESCRIPTION
SDIN4CLK
3
0
DESCRIPTION
SDIN3CLK
2
0
SDIN2CLK
1
0
Format
0
1
2
3
4
5
CS4382
SDIN1CLK
FIGURE
0
0
33
34
35
36
37
38