CS4382-KQ Cirrus Logic Inc, CS4382-KQ Datasheet - Page 29

• Manufacturer Part Number: CS4382-KQ
• Description: D/A Converter (D-A) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4382-KQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.5V
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• No. Of Channels: 8
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

to low transition on AD0/CS after power-up and af-
ter the control port is activated, SPI format will be
selected.
6.3
In I
Data is clocked into and out of the part by the clock,
SCL, with a clock to data relationship as shown in
Figure 7. The receiving device should send an ac-
knowledge (ACK) after each byte received. There
is no CS pin. Pin AD0 forms the partial chip ad-
dress and should be tied to VLC or GND as re-
quired. The upper 6 bits of the 7 bit address field
must be 001100.
Note: MCLK is required during all I
tions. Please see reference 4 for further details.
6.3.1
To communicate with the CS4382, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then fol-
lowed by the data to be written. To write multiple
registers, continue providing a clock and data,
waiting for the CS4382 to acknowledge between
each byte. To end the transaction, send a STOP
condition.
6.3.2
To communicate with the CS4382, initiate a
START condition of the bus. Next, send the chip
2
C Format, SDA is a bidirectional data line.
I
2
Writing in I
Reading in I
C Format
2
2
C Format
C Format
2
C transac-
address. The eighth bit of the address byte is the
R/W bit (high for a read). The contents of the reg-
ister pointed to by the MAP will be output after the
chip address. To read multiple registers, continue
providing a clock and issue an ACK after each
byte. To end the transaction, send a STOP condi-
tion.
6.4
In SPI format, CS is the CS4382 chip select signal,
CCLK is the control port bit clock, CDIN is the in-
put data line from the microcontroller and the chip
address is 0011000. CS, CCLK and CDIN are all
inputs and data is clocked in on the rising edge of
CCLK.
Note that the CS4382 is write-only when in SPI
format.
6.4.1
Figure 8 shows the operation of the control port in
SPI format. To write to a register, bring CS low.
The first 7 bits on CDIN form the chip address and
must be 0011000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
MAP. To write multiple registers, keep CS low and
continue providing clocks on CCLK. End the read
transaction by setting CS high.
SPI Format
Writing in SPI
CS4382
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