DSPIC30F1010-20E/SO Microchip Technology, DSPIC30F1010-20E/SO Datasheet - Page 131

• Manufacturer Part Number: DSPIC30F1010-20E/SO
• Description: 6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

12.15 Configuring a PWM Channel
Example 12-1 is a code example for configuring PWM
channel 1 to operate in complementary mode at 400
kHz, with a dead-time value of approximately 64 nsec.
It is assumed that the dsPIC30F1010/202X is operating
on the internal fast RC oscillator with PLL in the high-
frequency range (14.55 MHz input to the PLL,
assuming industrial temperature rated part).
12.16 Speed Limits of PWM Output
The PWM output I/O buffers, and any attached circuits
such as FET drivers and power FETs, have limited
slew-rate capability. For very small PWM duty cycles,
the PWM output signal is low-pass filtered; no pulse
makes it through all of the circuitry.
A similar effect happens for duty cycle values near
100%. Before 100% duty cycle is reached, the output
PWM signal appears to saturate at 100%.
Users need to take such behavior into account in their
applications. In normal power conversion applications,
duty cycle values near 0% or 100% are avoided
because to reach these values is to operate in a Dis-
continuous mode or a Saturated mode where the
control loop may be non functional.
12.17 PWM Special Event Trigger
The PWM module has a Special Event Trigger that
allows A/D conversions to be synchronized to the PWM
time base. The A/D sampling and conversion time can
be programmed to occur at any point within the PWM
period. The Special Event Trigger allows the user to
minimize the delay between the time when A/D conver-
sion results are acquired and the time when the duty
cycle value is updated.
The Special Event Trigger is based on the primary
PWM time base.
The PWM Special Event Trigger has one register
(SEVTCMP)
(SEVTPS<3:0> in PTCON) to control its operation. The
PTMR value that causes a Special Event Trigger is
loaded into the SEVTCMP register.
© 2006 Microchip Technology Inc.
Circuitry
and
four
additional
control
Preliminary
bits
12.17.1
The PWM module always produces Special Event Trig-
ger pulses. This signal can optionally be used by the
ADC module.
12.17.2
The PWM Special Event Trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVTPS<3:0> control bits in
the PTCON register.
The special event output postscaler is cleared on the
following events:
• Any write to the SEVTCMP register.
• Any device reset.
12.18 Individual PWM Triggers
The PWM module also features an additional ADC trig-
ger output for each PWM generator. This feature is very
useful when the PWM generators are operating in
Independent Time Base mode.
A block diagram of a trigger circuit is shown in
Figure 12-19. The user specifies a match value in the
TRIGx register. When the local time base counter value
matches the TRIGx value, an ADC trigger signal is
generated.
Trigger signals are always generated regardless of the
TRIGx value as long as the TRIGx value is less than or
equal to the PWM period value for the local time base.
If the TRGIEN bit is set in the PWMCONx register, then
an interrupt request is generated.
The individual trigger outputs can be divided per the
TRGDIV<2:0> bits in the TRGCONx registers, which
allows the trigger signals to the ADC to be generated
once for every 1, 2, 3 ..., 7 trigger events.
The trigger divider allows the user to tailor the ADC
sample rates to the requirements of the control loop.
dsPIC30F1010/202X
SPECIAL EVENT TRIGGER ENABLE
SPECIAL EVENT TRIGGER
POSTSCALER
DS70178C-page 129