DSPIC30F1010-20E/SO Microchip Technology, DSPIC30F1010-20E/SO Datasheet - Page 215

• Manufacturer Part Number: DSPIC30F1010-20E/SO
• Description: 6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 18-3 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table implies that all the
bits are negated prior to the action specified in the
condition column.
TABLE 18-3:
Table 18-4 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 18-4:
© 2006 Microchip Technology Inc.
Power-on Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from
Sleep
Clock Failure Trap
Trap Reset
Illegal Operation Trap
Note 1:
Power-on Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from
Sleep
Clock Failure Trap
Trap Reset
Illegal Operation Reset
Legend: u = unchanged
Note 1:
Condition
Condition
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
INITIALIZATION CONDITION FOR RCON REGISTER CASE 1
INITIALIZATION CONDITION FOR RCON REGISTER CASE 2
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
Program
PC + 2
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
Counter
Program
PC + 2
Counter
PC + 2
PC + 2
(1)
(1)
TRAPR
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP
0
0
0
0
0
0
0
0
0
1
0
0
u
u
u
u
u
u
u
u
1
u
Preliminary
IOPUWR
0
u
u
u
u
u
u
u
u
u
1
0
0
0
0
0
0
0
0
0
0
1
dsPIC30F1010/202X
EXTR SWR WDTO IDLE SLEEP
0
1
0
1
1
0
u
u
u
u
u
0
1
0
1
1
0
0
0
0
0
0
0
0
1
u
u
0
u
u
u
u
u
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
u
u
u
u
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
u
u
u
u
u
0
0
0
0
1
0
0
0
0
0
0
DS70178C-page 213
0
0
0
1
0
0
1
1
u
u
u
0
0
0
1
0
0
1
1
0
0
0
POR
POR
1
u
u
u
u
u
u
u
u
u
u
1
0
0
0
0
0
0
0
0
0
0