DSPIC30F2023-20E/PT Microchip Technology, DSPIC30F2023-20E/PT Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F2023-20E/PT
• Description: 12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x1
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2023-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 35
• Interface Type: I2C/SPI/UART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F1010/202X
12. ADC Shared Sample and Hold Circuit
13. Current Reset Mode
14. Output Compare Module
15. Output Compare Module in PWM Mode
16. Output Compare Module
17. SPI Module in Slave Select Mode
18. SPI Module in Frame Master Mode
19. SPI Module
20. UART Module
21. UART Module
22. UART Module
23. UART Module
DS80319D-page 2
Depending on conversion configuration, ADC
inputs that do not have dedicated sample and hold
circuits may produce inaccurate conversion results.
Setting the XPRES bit in the PWMCONx register
should enable a current-limit source to reset the
PWM period when the PWM generated is
configured in Independent Time Base mode. This
functionality is not working correctly.
The output compare module will produce a glitch
on the output when an I/O pin is initially set high
and the module is configured to drive the pin low at
a specified time.
The output compare module will miss one
compare event when the duty cycle register value
is updated from 0x0000 to 0x0001.
In Dual Compare Match mode, the OCx output is
not reset when the OCxR and OCxRS registers
are loaded with values having a difference of ‘1’.
The SPI module Slave Select functionality will not
work correctly.
The SPI module will fail to generate frame
synchronization pulses in Frame Master mode if
FRMDLY = 1.
The SMP bit does not have any effect when the
SPI module is configured for a 1:1 prescale factor
in Master mode.
If the Baud Rate Generator (BRG) register
contains an odd value and the parity option is
enabled, the module may falsely indicate parity
errors.
The Receive Buffer Overrun Error Status bit may
be set prematurely.
UART receptions may be corrupted in high baud
rate mode (BRGH = 1).
UTXISEL0 bit in the UxSTA register is always read
as zero regardless of the value written to it.
24. UART Module
25. UART Module
26. UART Module (IrDA
27. UART Module
28. I
29. I
30. I
31. I
32. MCLR pin
33. Decimal Adjust Instruction
34. Sleep Mode
35. PWM Module
36. PWM Module
The auto-baud feature does not work properly in
high baud rate mode (BRGH = 1).
When the auto-baud feature is enabled, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
The operation of the RXINV bit in the UxMODE
register is inverted.
The auto-baud feature measures baud rate
inaccurately for certain baud rate and clock speed
combinations.
The bus collision status bit does not get set when
a bus collision occurs during a Restart or Stop
event.
The I2CxTRN register can be written to even if a
write collision is detected.
The ACKSTAT bit does not reflect the status of a
transmission received from an I
The D_A status bit in the I2CxSTAT register does
not get set on a write to the I2CxTRN register by
an I
When the dsPIC
enabled, the MCLR pin does not operate correctly
in the event of a brown-out condition.
The decimal adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>).
Execution of the Sleep instruction (PWRSAV #0)
may cause incorrect program operation after the
device wakes up from Sleep. The current
consumption during Sleep may also increase
beyond the specifications listed in the device data
sheet.
The
temperatures below -20ºC.
In Push-Pull mode, with immediate updates
enabled, the PWM pins may become swapped.
2
2
2
2
C™ Module
C Module
C Module
C Module
2
C Slave device.
PWM
module
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DSC is operated with the PLL
© 2008 Microchip Technology Inc.
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C Slave device.
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