DSPIC30F2023-20E/PT Microchip Technology, DSPIC30F2023-20E/PT Datasheet - Page 4

• Manufacturer Part Number: DSPIC30F2023-20E/PT
• Description: 12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x1
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2023-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 35
• Interface Type: I2C/SPI/UART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F1010/202X
1. Module: Power Supply PWM: Dead Time
2. Module: Power Supply PWM: Duty Cycle
DS80319D-page 4
If
(DTC<1:0> = 0 or 1 in the PWMCONx register),
the minimum usable value that can be written to
the dead time registers, DTRx and ALTDTRx, is
0x0010. Writing a value less than 0x0010 will
cause either or both the PWMxH and PWMxL
outputs not to function. The minimum acceptable
dead time value is 0x0010. As a result of this
errata, the minimum usable dead time is 16 ns.
Dead time resolution is 4 ns for dead times greater
than 16 ns.
Work around
The
(DTC<1:0> = 2) or DTRx and ALTDRx must have
a value of 0x0010 or greater. If zero dead time is
required, configure the DTC<1:0> bits in the
PWMCONx register to specify no dead time.
The data sheet indicates that the power supply
PWM module has a 1.1 ns duty cycle resolution.
This is true for all values of PDCx except the
following:
1. 0x0010 < PDCx < 0x0040
2. (Period – 0x0040) < PDCx < (Period – 0x0010)
In these ranges, duty cycle resolution is 16 ns. The
PWM Period is either the Master Period, PTPER,
or the individual PWM generator period, PHASEx.
Work around
If possible, the system should be designed so that
the PWM generator will operate in the duty cycle
range where the 1.1 ns resolution is possible. For
operation outside this range, the design must take
into account the reduced resolution.
dead
dead
time
time
must
functionality
either
be
is
disabled
enabled
3. Module: Power Supply PWM: Special
4. Module: PWM Override Enable
Each PWM generator can be configured to
generate a trigger for the ADC module or a trigger
interrupt at any point during the PWM period. The
point in time during the PWM period that the trigger
is set is specified in the TRIGx register for PWM
Individual Trigger, or in the SEVTCMP register for
the Special Event Trigger. The minimum trigger
value in TRIGx or SEVTCMP is 0x0008. Values
below 0x0008 result in a PWM trigger not being
initiated at all. As a result, no ADC sampling or
trigger interrupt will occur.
Work around
If the Special Event Trigger or the Individual
Trigger is implemented, the user should perform a
check in firmware to make sure that TRIGx and/or
SEVTCMP is always greater than 0x0008 and less
than the PWM period.
The OVRDAT<1:0> bits in the IOCONx register
should determine the state of the PWMx output
pins when the OVRENH and OVRENL bits
(IOCONx<9:8>) are set. However, the PWM
override feature does not work correctly. The
PWMxH and PWMxL pins do not exhibit the state
specified by the OVRDAT<1:0> bits when only one
of the override bits (OVRENH or OVRENL) is set.
If both bits are set, the override state is exhibited
correctly on the PWMxL and PWMxH pins.
Work around
If override capability is desired on only one of the
PWM pin pairs, use the GPIO module to override
the PWM outputs. This can be done using the
PENH and PENL bits in the IOCONx register.
When the PENH/PENL bits in the IOCONx
register. When the PENH/PENL bits are cleared,
the GPIO module assumes control of the
PWMxH/L output pin. The GPIO module must be
setup in advance for the desired override output
states, and the pins must be configured as digital
outputs. This includes setting the PORTx and
TRISx registers correctly, which correspond to the
PWMxH and PWMxL pins.
Event Trigger and Individual
Trigger
© 2008 Microchip Technology Inc.