DSPIC30F2023-20E/PT Microchip Technology, DSPIC30F2023-20E/PT Datasheet - Page 7

• Manufacturer Part Number: DSPIC30F2023-20E/PT
• Description: 12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x1
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2023-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 35
• Interface Type: I2C/SPI/UART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9. Module: ADC Sample and Hold Timing
10. Module: ADC Interrupts
11. Module: ADC Module: Conversion Rate
12. Module: ADC Module: Shared Sample
© 2008 Microchip Technology Inc.
The dedicated ADC sample and hold circuits can
be triggered by signals from the PWM module. The
dsPIC30F1010/202X data sheet indicates that the
resolution of the PWM-ADC sample and hold
trigger timing is 8 ns. The existing implementation
has a 41.6 ns resolution. In other words, when the
PWM-ADC trigger is fired, an ADC sample may
occur 1 ns to 41.6 ns later.
Work around
None.
The dsPIC30F1010/202X data sheet specifies that
each ADC pin pair has its own interrupt vector.
These
dsPIC30F1010/202X Rev. A2 devices.
Work around
Each ADC pin pair can be configured to initiate a
global ADC interrupt by setting the corresponding
IRQENx bit in the ADCPCx register. The ADBASE
register can be used to create a jump table in the
global ADC interrupt which will execute the
appropriate ADC service routine for a particular
ADC pin pair. There is an ADBASE register code
example in the dsPIC30F1010/202X data sheet
which illustrates using the ADBASE register in this
way.
The data sheet indicates that the conversion rate
for the ADC module is 2.0 Msps. The ADC module
on the dsPIC30F1010/202X Rev. A2 silicon has a
maximum conversion rate of 1.5 Msps.
Work around
None.
The ADC inputs that do not have a dedicated
sample and hold circuit will yield inaccurate
conversion results unless the work around is
implemented. For dsPIC30F1010/202X devices,
the affected channels are AN1, AN3, AN5, AN7,
AN8, AN9, AN10 and AN11 (depending on
package). Additionally, this also applies to AN4
and AN6 on the dsPIC30F1010.
Work around
In the ADCON register, configure the ADC with
Order = 0 and SEQSAMP = 1. This configuration
allows for accurate conversion of the analog
channels which use the shared sample and hold
circuit.
interrupts
and Hold Circuit
do
not
work
on
the
13. Module: Current Reset Mode
14. Module: Output Compare Module
dsPIC30F1010/202X
Setting the XPRES bit in the PWMCONx register
should enable a current-limit source to reset the
PWM period in Independent Time Base mode.
This mode is not functioning correctly.
If the selected current-limit signal (either an analog
comparator or external signal) triggers after the
falling edge of PWMH, then the XPRES operation
functions correctly. The PWM deasserted time is
truncated and the PWM period is terminated early,
and a new PWM cycle begins.
If the selected current-limit signal (either an analog
comparator or external signal) triggers before the
falling edge of PWMH, the PWMH asserted time is
truncated, and the inactive time after the falling
edge PWMH remains constant.
The proper XPRES behavior is to ignore the
current-limit signal until the falling edge of the
PWM period.
This issue may not be a problem in applications
that control inductor current above a specified
minimum current level. When the inductor current
falls below the specified minimum value during the
PWMH off-time, the PWM period is truncated and
a new cycle begins to increase the inductor
current.
Work around
None.
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
• The output compare module is configured and
When these events occur, the output compare
module will drive the pin low for one instruction
cycle (T
Work around
None. However, the user may use a timer interrupt
and write to the associated PORT register to
control the pin manually.
high using the output compare module or a
write to the associated PORT register.
enabled to drive the pin low at some later time
(OCxCON = 0x0002 or OCxCON = 0x0003).
CY
) after the module is enabled.
DS80319D-page 7