DSPIC30F2023-20E/PT Microchip Technology, DSPIC30F2023-20E/PT Datasheet - Page 114

• Manufacturer Part Number: DSPIC30F2023-20E/PT
• Description: 12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x1
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2023-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 35
• Interface Type: I2C/SPI/UART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F1010/202X
REGISTER 12-4:
REGISTER 12-5:
DS70178C-page 112
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
Note 1: The minimum value for this register is 0x0008 and the maximum value is 0xFFEF.
FLTSTAT
HS/HC-0
R/W-0
R/W-0
R/W-0
DTC<1:0>
Master PWM Duty Cycle Value bits
FLTSTAT: Fault Interrupt Status
1 = Fault Interrupt is pending
0 = No Fault Interrupt is pending
This bit is cleared by setting FLTIEN = 0.
CLSTAT: Current-Limit Interrupt Status bit
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt enabled
0 = Fault interrupt disabled and FLTSTAT bit is cleared
HS/HC-0
CLSTAT
Note:
Note:
R/W-0
R/W-0
R/W-0
MDC: PWM MASTER DUTY CYCLE REGISTER
PWMCONx: PWM CONTROL REGISTER
Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt
Controller.
Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt
Controller.
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
TRGSTAT
HS/HC-0
R/W-0
R/W-0
U-0
—
FLTIEN
R/W-0
R/W-0
R/W-0
U-0
Preliminary
—
(1)
MDC<15:8>
MDC<7:0>
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
CLIEN
R/W-0
R/W-0
R/W-0
U-0
—
TRGIEN
R/W-0
R/W-0
R/W-0
U-0
—
© 2006 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
XPRES
R/W-0
R/W-0
R/W-0
R/W-0
ITB
MDCS
R/W-0
R/W-0
R/W-0
R/W-0
IUE
bit 8
bit 0
bit 8
bit 0