LM93CIMT National Semiconductor, LM93CIMT Datasheet - Page 81

• Manufacturer Part Number: LM93CIMT
• Description: Microprocessor Support IC
• Manufacturer: National Semiconductor

Specifications of LM93CIMT

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Supply Voltage Min: 3V
• Operating Temperature Min: 0��C
• Package / Case: 56-TSSOP
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register
Address
Register
Address
16.0 Registers
16.9.2 Register E5h S1 GPI Mask
16.9.3 Register E6h S1 Tach Mask
E5h
E6h
Read/
Write
R/W
Read/
Write
R/W
Bit
7:4
Register
S1 GPI
0
1
2
3
Name
Bit
Register
Mask
S1 Tach
0
1
2
3
4
5
6
7
Name
Mask
TACH1_S1_MSK
TACH2_S1_MSK
TACH3_S1_MSK
TACH4_S1_MSK
GPI0_S1_MSK
GPI1_S1_MSK
GPI2_S1_MSK
GPI3_S1_MSK
GPI4_S1_MSK
GPI5_S1_MSK
GPI6_S1_MSK
GPI7_S1_MSK
(Continued)
GPI7_S1
Name
Name
_MSK
RES
Bit 7
Bit 7
Bit 6
GPI6_S1
_MSK
Bit 6
RES
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 5
R
GPI5_S1
_MSK
If set, GPI0 errors are masked in S1 sleep state.
If set, GPI1 errors are masked in S1 sleep state.
If set, GPI2 errors are masked in S1 sleep state.
If set, GPI3 errors are masked in S1 sleep state.
If set, GPI4 errors are masked in S1 sleep state.
If set, GPI5 errors are masked in S1 sleep state.
If set, GPI6 errors are masked in S1 sleep state.
If set, GPI7 errors are masked in S1 sleep state.
Bit 5
Bit 4
If set, Tach1 errors are masked in S1 sleep state.
If set, Tach2 errors are masked in S1 sleep state.
If set, Tach3 errors are masked in S1 sleep state.
If set, Tach4 errors are masked in S1 sleep state.
Reserved
81
GPI4_S1
TACH4_S1
_MSK
Bit 4
_MSK
Bit 3
GPI3_S1
Description
_MSK
Description
Bit 3
TACH3_S1
_MSK
Bit 2
GPI2_S1
_MSK
Bit 2
TACH2_S1
_MSK
Bit 1
GPI1_S1
_MSK
Bit 1
TACH1_S1
_MSK
GPI0_S1
Bit 0
_MSK
Bit 0
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Default
Default
Value
Value
0Fh
FFh