PIC18F2423-I/ML Microchip Technology, PIC18F2423-I/ML Datasheet
PIC18F2423-I/ML
Specifications of PIC18F2423-I/ML
Related parts for PIC18F2423-I/ML
PIC18F2423-I/ML Summary of contents
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... Refer to Section 6.0 applies to Requirements for Program/Verify Test Mode” for additional hardware parameters. 2.2 Pin Diagrams The pin diagrams for the PIC18F2423/2523/4423/4523 family are shown in Figure 2-1 and Figure 2-2. During Programming Pin Type P Programming Enable P Power Supply ...
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... PIC18F2423/2523/4423/4523 FIGURE 2-1: PIC18F2423/2523/4423/4523 FAMILY PIN DIAGRAMS 28-Pin SDIP, SOIC (300 MIL) MCLR/V PP OSC1 OSC2 28-Pin QFN 40-Pin PDIP (600 MIL) MCLR/V PP DS39759A-page 2 /RE3 28 1 RA0 27 2 RA1 26 3 RA2 4 25 RA3 5 24 RA4 6 23 RA5 RC0 11 18 RC1 17 12 RC2 ...
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... FIGURE 2-2: PIC18F2423/2523/4423/4523 FAMILY PIN DIAGRAMS 44-Pin TQFP RC7 RD4 RD5 RD6 RD7 RB0 RB1 RB2 RB3 44-Pin QFN RC7 RD4 RD5 RD6 RD7 RB0 RB1 RB2 © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 ICV RC0 2 OSC2 OSC1 PIC18F4423 PIC18F4523 27 RE2 RE1 ...
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... PIC18F2423/2523/4423/4523 2.3 Memory Maps For PIC18F2523/4523 devices, the code memory space extends from 000000h to 007FFFh (32 Kbytes) in four 8-Kbyte blocks. Addresses 000000h through 0007FFh, however, define a “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space ...
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... For PIC18F2423/4423 devices, the code memory space extends from 000000h to 003FFFh (16 Kbytes) in two 8-Kbyte blocks. Addresses 000000h through 0003FFh, however, define a “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. ...
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... Section 5.0 “Configuration Word”. These device ID bits read out normally, even after code protection. FIGURE 2-5: CONFIGURATION AND ID LOCATIONS FOR PIC18F2423/2523/4423/4523 DEVICES 000000h Code Memory 01FFFFh Unimplemented Read as ‘0’ ...
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... Configuration Bits Done Note 1: Selected devices only, see Section 3.3 “Data EEPROM Programming”. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 2.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode As shown in Figure 2-7, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/V (high voltage) ...
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... PIC18F2423/2523/4423/4523 2.6 Entering and Exiting Low-Voltage ICSP Program/Verify Mode When the LVP Configuration bit is ‘1’ (see Section 5.3 “Single-Supply ICSP Programming”), Low-Voltage ICSP mode is enabled. As shown in Figure 2-9, Low-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low, placing a logic ...
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... FIGURE 2-11: TABLE WRITE, POST-INCREMENT TIMING (1101) P2 P2A P2B PGC PGD 4-Bit Command © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 16-Bit Data Payload PGD = Input P5A Fetch Next 4-Bit Command DS39759A-page 9 ...
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... PIC18F2423/2523/4423/4523 3.0 DEVICE PROGRAMMING Programming includes the ability to erase or write the various memory regions within the device. In all cases except high-voltage ICSP Bulk Erase, the EECON1 register must be configured in order to operate on a particular memory region. When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1< ...
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... PGC must be held low for the time “Data specified by parameter P10 to allow high-voltage discharge of the memory array. The code sequence to Row Erase a PIC18F2423/2523/ 4423/4523 device is shown in Table 3-3. The flowchart shown in Figure 3-3 depicts the logic necessary to completely device. The timing diagram that details the Start Programming command and parameters P9 and P10 is shown in Figure 3-5 ...
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... PIC18F2423/2523/4423/4523 TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE 4-Bit Data Payload Command Step 1: Direct access to code memory and enable writes. 0000 8E A6 0000 9C A6 0000 84 A6 Step 2: Point to first row in code memory. 0000 6A F8 0000 6A F7 0000 6A F6 Step 3: Enable erase and erase single row. ...
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... To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented each iteration of the loop. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The code sequence to program a PIC18F2423/2523/ 4423/4523 device is shown in Table 3-5. The flowchart, shown in Figure 3-4, depicts the logic necessary to completely device ...
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... PIC18F2423/2523/4423/4523 FIGURE 3-4: PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 FIGURE 3-5: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111 PGC P5 PGD 4-Bit Command 16-Bit Data Payload DS39759A-page 14 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? ...
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... Step 7: Disable writes. 0000 94 A6 © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4.2 “Verify Code Memory and ID Locations”) and buffered. Modifications can be made on this buffer ...
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... PIC18F2423/2523/4423/4523 3.3 Data EEPROM Programming Data EEPROM is accessed one byte at a time via an Address Pointer (register pair EEADRH:EEADR) and a data latch (EEDATA). Data EEPROM is written by loading EEADRH:EEADR with the desired memory location, EEDATA with the data to be written and initiat- ing a memory write by appropriately configuring the EECON1 register ...
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... Step 7: Hold PGC low for time P10. Step 8: Disable writes. 0000 94 A6 Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on shift out data timing. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW < ...
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... PIC18F2423/2523/4423/4523 3.4 ID Location Programming The ID locations are programmed much like the code memory. The ID registers are mapped in addresses 200000h through 200007h. These locations read out normally even after code protection. Note: The user only needs to fill the first 8 bytes of the write buffer in order to write the ID locations ...
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... LSB Delay P9 and P10 Time for Write Done © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 3.6 Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (‘1111’) is used, but only 8 bits of the following 16-bit payload will be written ...
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... PIC18F2423/2523/4423/4523 4.0 READING THE DEVICE 4.1 Read Code Memory, ID Locations and Configuration Bits Code memory is accessed one byte at a time via the 4-bit command, ‘1001’ (table read, post-increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially output on PGD ...
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... No code memory verified? Yes © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified. The post-increment feature of the table read 4-bit command may not be used to increment the Table Pointer beyond the code memory space ...
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... PIC18F2423/2523/4423/4523 4.3 Verify Configuration Bits A configuration address may be read and output on PGD via the 4-bit command, ‘1001’. Configuration data is read and written in a byte-wise fashion not necessary to merge two bytes into a word prior to a compare. The result may then be immediately compared to the appropriate configuration data in the programmer’ ...
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... FFh except the Configuration bits. Unused (reserved) Configuration bits will read ‘0’ (programmed). Refer to Table 5-1 for blank configuration expect data for the various PIC18F2423/2523/4423/ 4523 devices. Given that Blank Checking is merely code and data EEPROM verification with FFh expect data, refer to Section 4.4 “ ...
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... DEV3 DEV2 (2) 3FFFFFh DEVID2 DEV11 DEV10 Legend unknown unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F2423/4423 devices; maintain this bit set. 2: DEVID registers are read-only and cannot be programmed by the user. TABLE 5-2: DEVICE ID VALUE Device PIC18F2423 PIC18F2523 PIC18F4423 ...
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... TABLE 5-3: PIC18F2423/2523/4423/4523 BIT DESCRIPTIONS Configuration Bit Name Words IESO CONFIG1H FCMEN CONFIG1H FOSC3:FOSC0 CONFIG1H BORV1:BORV0 CONFIG2L BOREN1:BOREN0 CONFIG2L PWRTEN CONFIG2L WDPS3:WDPS0 CONFIG2H WDTEN CONFIG2H © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Description Internal External Switchover bit 1 = Internal External Switchover mode enabled ...
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... PIC18F2423/2523/4423/4523 TABLE 5-3: PIC18F2423/2523/4423/4523 BIT DESCRIPTIONS (CONTINUED) Configuration Bit Name Words MCLRE CONFIG3H LPT1OSC CONFIG3H PBADEN CONFIG3H CCP2MX CONFIG3H DEBUG CONFIG4L XINST CONFIG4L LVP CONFIG4L STVREN CONFIG4L CP3 CONFIG5L CP2 CONFIG5L CP1 CONFIG5L CP0 CONFIG5L CPD CONFIG5H CPB CONFIG5H WRT3 CONFIG6L ...
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... TABLE 5-3: PIC18F2423/2523/4423/4523 BIT DESCRIPTIONS (CONTINUED) Configuration Bit Name Words WRT2 CONFIG6L WRT1 CONFIG6L WRT0 CONFIG6L WRTD CONFIG6H WRTB CONFIG6H WRTC CONFIG6H EBTR3 CONFIG7L EBTR2 CONFIG7L EBTR1 CONFIG7L EBTR0 CONFIG7L EBTRB CONFIG7H DEV11:DEV4 DEVID2 DEV3:DEV0 DEVID1 REV3:REV0 DEVID1 © 2005 Microchip Technology Inc. ...
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... Embedding Data EEPROM Information In the HEX File To allow portability of code, a PIC18F2423/2523/4423/ 4523 programmer is required to read the data EEPROM information from the hex file. If data EEPROM information is not present, a simple warning message should be issued. Similarly, when saving a hex file, all data EEPROM information must be included ...
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... Device PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523 Legend: Shaded cells are unimplemented. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Ending Address Block 0 Block 1 Block 2 Block 3 001FFF 003FFF — — 001FFF 003FFF 005FFF 007FFF 001FFF 003FFF — — 001FFF 003FFF 005FFF 007FFF Configuration Word (CONFIGxx) ...
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... PIC18F2423/2523/4423/4523 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25°C is recommended Param Sym Characteristic No. D110 V High-Voltage Programming Voltage on IHH MCLR/V /RE3 PP D110A V Low-Voltage Programming Voltage on IHL MCLR/V /RE3 PP D111 V Supply Voltage During Programming DD D112 I Programming Current on MCLR/V ...
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... T CY specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. 2: When ICPORT = 1, this specification also applies to ICV 3: At 0°C-50°C. © 2005 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Min Max 4 /RE3 ↑ /RE3 ↑ ...
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... PIC18F2423/2523/4423/4523 NOTES: DS39759A-page 32 © 2005 Microchip Technology Inc. ...
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... PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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