PIC18F2423-I/ML Microchip Technology, PIC18F2423-I/ML Datasheet - Page 7

• Manufacturer Part Number: PIC18F2423-I/ML
• Description: 16KB, Flash, 768bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2423-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.4
Figure 2-6 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the code memory, ID locations and data EEPROM
are programmed (selected devices only, see Section 3.3
“Data EEPROM Programming”). These memories are
then verified to ensure that programming was successful.
If no errors are detected, the Configuration bits are then
programmed and verified.
FIGURE 2-6:
© 2005 Microchip Technology Inc.
Note 1:
High-Level Overview of the
Programming Process
Selected devices only, see Section 3.3
“Data EEPROM Programming”.
Program Data EE
Configuration Bits
Program Memory
Configuration Bits
Verify Program
Perform Bulk
Program IDs
Verify Data
Verify IDs
HIGH-LEVEL
PROGRAMMING FLOW
Program
Erase
Verify
Done
Start
(1)
PIC18F2423/2523/4423/4523
2.5
As shown in Figure 2-7, the High-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low and then raising MCLR/V
(high voltage). Once in this mode, the code memory,
data EEPROM (selected devices only, see Section 3.3
“Data EEPROM Programming”), ID locations and
Configuration bits can be accessed and programmed in
serial fashion. Figure 2-8 shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-7:
FIGURE 2-8:
MCLR/V
V
PGD
PGC
MCLR/V
D110
DD
V
PGD
PGC
DD
Entering and Exiting High-Voltage
ICSP Program/Verify Mode
D110
PP
PP
/RE3
/RE3
PGD = Input
PGD = Input
P13
P1
ENTERING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
EXITING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
P16
P1
P12
P17
DS39759A-page 7
PP
/RE3 to V
IHH