PIC18F2423-I/ML Microchip Technology, PIC18F2423-I/ML Datasheet - Page 18

• Manufacturer Part Number: PIC18F2423-I/ML
• Description: 16KB, Flash, 768bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2423-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2423/2523/4423/4523
3.4
The ID locations are programmed much like the code
memory. The ID registers are mapped in addresses
200000h through 200007h. These locations read out
normally even after code protection.
TABLE 3-8:
DS39759A-page 18
Step 1: Direct access to code memory and enable writes.
Step 2: Load write buffer with 8 bytes and write.
Note:
Command
0000
0000
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
4-Bit
ID Location Programming
The user only needs to fill the first 8 bytes
of the write buffer in order to write the ID
locations.
8E A6
9C A6
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
00 00
WRITE ID SEQUENCE
Data Payload
BSF
BCF
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
EECON1, EEPGD
EECON1, CFGS
Table 3-8 demonstrates the code sequence required to
write the ID locations.
In order to modify the ID locations, refer to the method-
ology described in Section 3.2.1 “Modifying Code
Memory”. As with code memory, the ID locations must
be erased before being modified.
Core Instruction
© 2005 Microchip Technology Inc.