S29AL016D90TFI020 Spansion Inc., S29AL016D90TFI020 Datasheet - Page 12

• Manufacturer Part Number: S29AL016D90TFI020
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of S29AL016D90TFI020

• Memory Size: 16Mbit
• Ic Interface Type: Parallel
• Access Time: 90ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Peak Reflow Compatible (260 C): Yes
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
12
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V
V
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the
specification.
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the
system. I
current specification.
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the system drives the RESET# pin to V
t
data output pins, and ignores all read/write attempts for the duration of the RE-
SET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of t
The system can read data t
Refer to the
for the timing diagram.
RP
IH
, the device immediately terminates any operation in progress, tristates all
.) If CE# and RESET# are held at V
IL
SS
±0.3 V, the device draws CMOS standby current (I
but not within V
DC Characteristics
CC4
READY
AC Characteristics
in the
CC
(during Embedded Algorithms). The system can thus monitor RY/
± 0.3 V. (Note that this is a more restricted voltage range than
DC Characteristics
SS
±0.3 V, the standby current will be greater.
table, I
RH
after the RESET# pin returns to V
tables for RESET# parameters and to
CE
CC3
) for read access when the device is in either
S29AL016D
P r e l i m i n a r y
table represents the automatic sleep mode
and I
IH
READY
, but not within V
CC4
(not during Embedded Algorithms).
represents the standby current
IL
CC4
for at least a period of
CC
). If RESET# is held
± 0.3 V, the device
IH
.
Figure 14
ACC
S29AL016D_00_A2 December 17, 2004
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