USBN9604-28MX National Semiconductor, USBN9604-28MX Datasheet - Page 41

• Manufacturer Part Number: USBN9604-28MX
• Description: IC,Bus Controller,SOP,28PIN
• Manufacturer: National Semiconductor

Specifications of USBN9604-28MX

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

www.national.com
7.0 Register Set
DERR
DMA Error. This bit is set to indicate that a packet has not been received or transmitted correctly. It is also set if the TOGGLE
bit in the RXSx/TXSx register does not equal the NTGL bit in the DMAEV register after packet reception/transmission. (Note
that this comparison is made before the NTGL bit changes state due to packet transfer).
For receiving, DERR is equivalent to RX_ERR. For transmitting, it is equivalent to TX_DONE (set) and ACK_STAT (not set).
If the AEH bit in the DMA Error Count (DMAERR) register is set, DERR is not set until DMAERRCNT in the DMAERR register
is cleared, and another error is detected. Errors are handled as specified in the DMAERR register.
DCNT
DMA Count. This bit is set when the DMA Count (DMACNT) register is 0 (see the DMACNT register for more information).
DSIZ
DMA Size. This bit is only significant for DMA receive operations. It indicates that a packet has been received which is less
than the full length of the FIFO. This normally indicates the end of a multi-packet transfer.
NTGL
Next Toggle. This bit determines the toggle state of the next data packet sent (if transmitting), or the expected toggle state
of the next data packet (if receiving). This bit is initialized by writing to the DTGL bit of the DMACNTRL register. It then chang-
es state with every packet sent or received on the endpoint presently selected by DSRC2-0. If DTGL write operation occurs
simultaneously with the bit update operation, the write takes precedence.
If transmitting, whenever ADMA operations are in progress the DTGL bit overrides the corresponding TOGGLE bit in the
TXCx register. In this way, the alternating data toggle occurs correctly on the USB.
Note that there is no corresponding mask bit for this event because it is not used to generate interrupts.
7.2.8
Any bit set to 1 in this register enables automatic setting of the DMA bit in the ALTEV register when the respective event in
the DMAEV register occurs. Otherwise, setting the DMA bit is disabled. For a description of bits 0 to 3, see the DMAEV reg-
ister.
•
•
•
•
If the ADMA bit is cleared (but DEN remains set). In this case, the current operation (if any) is completed. This means
that any data in the FIFO is either transmitted or transferred to memory by DMA (if receiving). The DSHLT bit is set only
after this has occurred. Note that since DEN remains set, it may need to be cleared later. This commonly is done inside
the DSHLT interrupt handler.
If the DEN bit is cleared (ADMA may either remain set, or may be cleared at the same time). This ceases all DMA oper-
ations and immediately sets the DSHLT bit. If there is data in the FIFOs, it is retained but not transmitted.
If the firmware attempts to read the FIFO (if receiving) or write to the FIFO (if transmitting). This ceases all DMA opera-
tions and immediately sets the DSHLT bit. The read or write operation may not succeed since this operation is likely to
corrupt the FIFO and lose some data.
If the firmware attempts to read to/write from the corresponding EPCx, TXCx, RXCx, TXSx, or RXSx registers (when
DEN and ADMA in the DMACNTRL register are both set). This halts all DMA operations and immediately sets the
DSHLT bit. The read or write operation is not effected.
DMA Mask Register (DMAMSK)
bit 7
(Continued)
bit 6
-
-
bit 5
bit 4
40
DSIZ
bit 3
r/w
0
DCNT
bit 2
r/w
0
DERR
bit 1
r/w
DSHLT
bit 0
r/w
0