USBN9604-28M National Semiconductor, USBN9604-28M Datasheet
USBN9604-28M
Specifications of USBN9604-28M
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USBN9604-28M Summary of contents
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... May 1998 USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support General Description The USBN9603/4 are integrated, USB Node controllers. Other than the reset mechanism for the clock generation cir- cuit, these two devices are identical. All references to “the device” ...
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Features Full-speed USB node device Integrated USB transceiver Supports 24 MHz oscillator circuit with internal 48 MHz clock generation circuit Programmable clock generator Serial Interface Engine (SIE) consisting of Physical Layer Interface (PHY) and Media Access Controller (MAC), USB Specification ...
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Table of Contents Signal/Pin Connection and Description 1.0 1.1 CONNECTION DIAGRAMS ........................................................................................................ 6 1.2 DETAILED SIGNAL/PIN DESCRIPTIONS .................................................................................. 7 1.2.1 Power Supply ................................................................................................................ 7 1.2.2 Oscillator, Clock and Reset ........................................................................................... 7 1.2.3 USB Port ....................................................................................................................... 8 1.2.4 Microprocessor Interface ............................................................................................... ...
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Table of Contents (Continued) 7.1.2 Clock Configuration Register (CCONF)...................................................................... 31 7.1.3 Revision Identifier (RID) .............................................................................................. 31 7.1.4 Node Functional State Register (NFSR) ..................................................................... 32 7.1.5 Main Event Register (MAEV) ....................................................................................... 32 7.1.6 Main Mask Register (MAMSK) .................................................................................... 33 7.1.7 Alternate ...
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Table of Contents (Continued) 7.3 REGISTER MAP ........................................................................................................................ 50 Device Characteristics 8.0 8.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................ 52 8.2 DC ELECTRICAL CHARACTERISTICS ................................................................................... 52 8.3 AC ELECTRICAL CHARACTERISTICS .................................................................................... 53 8.4 PARALLEL INTERFACE TIMING (MODE1-0 = 00B) ................................................................ 54 8.5 ...
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Signal/Pin Connection and Description 1.1 CONNECTION DIAGRAMS RESET AGND www.national.com 28-Pin CSP USBN9603/4SLB WR/SK ...
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... Reset. Active low, assertion of RESET indicates a hardware reset, which causes all registers in the device to revert to their reset values. In the USBN9604, the hardware reset action is identical to a power-on reset. Signal condition- ing is provided on this input to allow use of a simple, RC power-on reset circuit. ...
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Signal/Pin Connection and Description Component Resistor R2 Capacitor C1 Capacitor C2 External Elements Choose C1 and C2 capacitors (see Figure 1) to match the crystal’s load capacitance. The load capacitance C the crystal is comprised series ...
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Signal/Pin Connection and Description I WR Write. Active low write strobe, parallel interface SK MICROWIRE Shift Clock. Mode Address Bus Line. Mode 0, parallel interface ALE Address Latch Enable. Mode 1, parallel interface SI MICROWIRE ...
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Functional Overview The device is a Universal Serial Bus (USB) Node controller compatible with USB Specification, 1.0 and 1.1. It integrates onto a single IC the required USB transceiver with a 3.3V regulator, the Serial Interface Engine (SIE), USB ...
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Functional Overview (Continued) CS D7-0/AD7-0/SO A0/ALE/SI Endpoint/Control FIFOs Control SIE Transceiver D+ RD WR/SK DACK DRQ Microcontroller Interface (Parallel and Serial) Status RX TX Media Access Controller (MAC) Physical Layer Interface (PHY) VReg Upstream Port D- Figure 2. USBN9603/4 ...
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Functional Overview 2.4 ENDPOINT PIPE CONTROLLER (EPC) The EPC provides the interface for USB function endpoints. An endpoint is the ultimate source or sink of data. An endpoint pipe facilitates the movement of data between USB and memory, and ...
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Parallel Interface The parallel interface allows the device to function as a CPU or microcontroller peripheral. This interface type and its ad- dressing mode (multiplexed or non-multiplexed) is determined via device input pins MODE0 and MODE1. 3.1 NON-MULTIPLEXED MODE ...
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Parallel Interface (Continued) 3.1.1 Standard Access Mode The standard access sequence for non-multiplexed mode is to write the address to the ADDR register and then read or write the data from/to the DATA_OUT/DATA_IN register. The DATA_OUT register is updated ...
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Parallel Interface (Continued) 3.2 MULTIPLEXED MODE Multiplexed mode uses the control pins CS, RD, WR, the address latch enable signal ALE and the bidirectional address data bus AD7-0 as shown in Figure 6. This mode is selected by tying ...
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Direct Memory Access (DMA) Support The device supports DMA transfers with an external DMA controller from/to endpoints This mode uses the device pins DRQ and DACK in addition to the parallel interface pins ...
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Direct Memory Access (DMA) Support 4.2 AUTOMATIC DMA MODE (ADMA) The ADMA mode allows the CPU to transfer independently large bulk or isochronous data streams to or from the USB bus. The application’s DMA controller, together with the ADMA ...
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Direct Memory Access (DMA) Support DRQ DACK WR D7-0 DRQ DACK RD D7-0 www.national.com (Continued) Input Figure 12. DMA Write to USBN9603/4 Output Figure 13. DMA Read from USBN9603/4 18 ...
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MICROWIRE/PLUS Interface The MICROWIRE/PLUS interface allows the device to function as a CPU or microcontroller peripheral via a serial interface. This mode is selected by pulling the MODE1 pin high and the MODE0 pin low. The MICROWIRE/PLUS mode uses ...
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MICROWIRE/PLUS Interface 5.2 READ AND WRITE TIMING Data is read by shifting in the 2-bit command (CMD and the 6-bit address, RADDR or WADDR) while simultaneously shifting out read data from the previous address. Data can be written in ...
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MICROWIRE/PLUS Interface CMD=11 SO (Continued) 8 Cycles 8 Cycles ADDR Write Data Undefined Data Read Data Figure 17. Burst Write Timing 21 8 Cycles Write Data Read Data www.national.com ...
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Functional Description 6.1 FUNCTIONAL STATES 6.1.1 Line Condition Detection At any given time, the device is in one of the following states (see Section 6.1.2 for the functional state transitions): • NodeOperational Normal operation • NodeSuspend Device operation suspended ...
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Functional Description NodeOperational suspend_det & set_suspend resume_det & set_oper NodeSuspend 11b local_event & sd5_detect & Notes: 1. When the node is not in NodeOperational state, all registers are frozen with the exception of the endpoint con- troller state machines, ...
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Functional Description 6.2 ENDPOINT OPERATION 6.2.1 Address Detection Packets are broadcast from the host controller to all the nodes on the USB network. Address detection is implemented in hardware to allow selective reception of packets and to permit optimal ...
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Functional Description Endpoint No two endpoints in the same direction are programmed with the same endpoint number and both are enabled, data is re- ceived or transmitted to/from the endpoint with ...
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Functional Description A packet written to the FIFO is transmitted token for the respective endpoint is received error condition is de- tected, the packet data remains in the FIFO and transmission is retried with ...
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Functional Description TCOUNT Transmit FIFO Count. This value indicates how many empty bytes can be filled within the transmit FIFO. This value is ac- cessible by firmware via the TxSx register. Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3) The ...
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Functional Description 6.2.3 Programming Model Figure 23 illustrates the register hierarchy for event reporting. . FWEV 6.3 POWER SAVING MODES To minimize the power consumption of the USB node, the device can be set to a static Halt mode. ...
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... In the USBN9603, however, assertion of the RESET input does cause all registers to revert to their reset values, including CCONF, which then forces the CLKOUT signal to its default of 4 MHz. In the USBN9604, assertion of the RESET input causes the clock generation circuit to be reset as with the power-on reset. As part of the clock generation reset, a delay of 2 sertion of the RESET input also causes all registers to revert to their reset values, including CCONF, which then forces the CLKOUT signal to its default of 4 MHz ...
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Register Set The device has a set of memory-mapped registers that can be read from/written to control the USB interface. Some register bits are reserved; reading from these bits returns undefined data. Reserved register bits should always be written ...
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Register Set (Continued) 7.1.2 Clock Configuration Register (CCONF) bit 7 bit 6 CODIS 0 r/w CLKDIV External Clock Divisor. The power-on reset and a hardware reset configure the divisor MHz output clock. frequency = 48 ...
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Register Set (Continued) 7.1.4 Node Functional State Register (NFSR) bit 7 bit 6 NFS Node Functional State. The firmware should initiate all required state transitions according to the respective status bits in the Alternate Event (ALTEV) register. The valid ...
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Register Set (Continued) TX_EV Transmit Event. This bit is set if any of the unmasked bits in the Transmit Event (TXEV) register (TXFIFOx or TXUNDRNx) is set. Therefore, it indicates that an IN transaction has been completed. This bit ...
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Register Set (Continued) EOP End of Packet. A valid EOP sequence was detected on the USB used when this device has initiated a Remote wake-up sequence to indicate that the Resume sequence has been acknowledged and completed ...
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Register Set (Continued) 7.1.10 Transmit Mask Register (TXMSK) When set and the corresponding bit in the TXEV register is set, TX_EV in the MAEV register is set. When cleared, the cor- responding bit in the TXEV register does not ...
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Register Set (Continued) 7.1.13 NAK Event Register (NAKEV) bit 7 bit 6 RXFIFO3 RXFIFO2 RXFIFO1 OUT3 Set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the Function Ad- dress, ...
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Register Set (Continued) 7.2.2 FIFO Warning Mask Register (FWMSK) When set and the corresponding bit in the FWEV register is set, WARN in the MAEV register is set. When cleared, the cor- responding bit in the FWEV register does ...
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Register Set (Continued) 7.2.5 Function Address Register (FAR) This register sets the device function address. The different endpoint numbers are set for each endpoint individually via the Endpoint Control registers. bit 7 bit 6 AD_EN 0 0 r/w AD ...
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Register Set (Continued) A DMA request from a transmit endpoint is activated until the request condition clears. If DMOD is set to 0, DMA requests are issued either until the firmware reads the respective Transmit Status (TXSx) register, thus ...
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Register Set (Continued) • If the ADMA bit is cleared (but DEN remains set). In this case, the current operation (if any) is completed. This means that any data in the FIFO is either transmitted or transferred to memory ...
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Register Set (Continued) 7.2.9 Mirror Register (MIR) This is a read only register. Since reading it does not alter the state of the TXSx or RXSx register to which it points, the firmware can freely check the status of ...
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Register Set (Continued) AEH Automatic Error Handling. This bit has two different meanings, depending on the current transaction mode: Non-Isochronous mode This mode is used for bulk, interrupt and control transfers. Setting AEH in this mode enables automatic handling ...
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Register Set (Continued) 7.2.13 Endpoint Control 0 Register (EPC0) This register controls mandatory Endpoint Control 0. bit 7 bit 6 STALL DEF 0 0 r/w r/w EP Endpoint. This field holds the 4-bit endpoint address. For Endpoint 0, these ...
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Register Set (Continued) 7.2.15 Transmit Command 0 Register (TXC0) bit 7 bit 6 Reserved - - TX_EN Transmission Enable. This bit enables data transmission from the FIFO cleared by the chip after transmitting a single packet, or ...
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Register Set (Continued) RX_LAST Receive Last Bytes. Indicates that an ACK was sent upon completion of a successful receive operation. This bit is un- changed for zero length packets cleared when this register is read. TOGGLE This ...
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Register Set (Continued) 7.2.20 Endpoint Control X Register (EPC1 to EPC6) Each unidirectional endpoint has an EPCx register with the bits defined below. bit 7 bit 6 STALL Reserved Endpoint. This field holds the ...
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Register Set (Continued) For ISO operation, this bit is set if a frame number LSB match (see “IGN_ISOMSK” bit in Section 7.2.22) occurs, and data was sent in response token. Otherwise, this bit is reset, the ...
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Register Set (Continued) IGN_ISOMSK Ignore ISO Mask. This bit has an effect only if the endpoint is set to be isochronous. If set, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. ...
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Register Set (Continued) For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint. This bit is reset reading the RXSx register. SETUP This bit ...
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Register Set (Continued) 7.2.26 Receive Data X Register (RXD1, RXD2, RXD3) Each of the three Receive Endpoint FIFOs has one Receive Data register with the bits defined below. bit 7 bit 6 RXFD Receive FIFO Data Byte. See “Receive ...
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Register Set (Continued) Address 0x18 0x19 0x1A 0x1B 0x1C - 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B ...
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Device Characteristics 8.1 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate limits beyond which damage to the device may occur. Supply Voltage DC Input Voltage DC Output Voltage Storage Temperature Lead Temperature (Soldering 10 seconds) 1 ESD Rating 1. Human ...
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Device Characteristics Symbol Parameter V Input Low Voltage IL I Input Low Current IL I Input High Current IH I Tri-state Leakage OZ Oscillator Input/Output Signals (XTALIN, XTALOUT) V Input High Switching Level IH V Input Low Switching Level ...
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Device Characteristics Note: CKI in the following tables refers to the internal clock of the device and not to the signal frequency applied at XIN. 8.4 PARALLEL INTERFACE TIMING (MODE1 (3.0V< V < 5.5V, 0˚C < TA< ...
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Device Characteristics D7-0 Input Figure 26. Non-Multiplexed Mode Write Timing Note: The setup and hold times t Both signals may switch at the same time. 8.5 PARALLEL INTERFACE TIMING (MODE1 (3.0V< V < 5.5V, ...
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Device Characteristics ALE CS RD AD7-0 Figure 27. Multiplexed Mode Interface Read Timing ALE CS WR AD7-0 Figure 28. Multiplexed Mode Interface Write Timing www.national.com (Continued CLAL t ALRH AVAL RLDV AHAL ADDR ...
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Device Characteristics 8.6 DMA SUPPORT TIMING (3.0V< V < 5.5V, 0˚C < TA< +70˚C, unless otherwise specified) CC Symbol Parameter t Request High to ACK Low RHAL t ACK Low to Write Low ALWL t Write Pulse Width WW ...
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Device Characteristics 8.7 MICROWIRE INTERFACE TIMING (MODE1 Symbol Parameter Cycle Time SKC t Time between two consecutive clock cycles t Serial Input Hold Time SIH t Serial Output Valid Time SOV ...
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Physical Dimensions Inches (millimeters) unless otherwise noted Laminate Substrate Based Package Order Number USBN9603/4SLB See NS Package Number SLB28AA Molded SO Wide Body Package (WM) Order Number USBN9603/4-28M See NS Package Number M28B 59 www.national.com ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...