USBN9604-28M National Semiconductor, USBN9604-28M Datasheet - Page 47

• Manufacturer Part Number: USBN9604-28M
• Description: Special Function IC
• Manufacturer: National Semiconductor

Specifications of USBN9604-28M

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 28-WSOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.0 Register Set
For ISO operation, this bit is set if a frame number LSB match (see “IGN_ISOMSK” bit in Section 7.2.22) occurs, and data
was sent in response to an IN token. Otherwise, this bit is reset, the FIFO is flushed and TX_DONE is set.
This bit is also cleared when this register is read.
TX_URUN
Transmit FIFO Underrun. This bit is set if the transmit FIFO becomes empty during a transmission, and no new data is written
to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is reset when this
register is read.
7.2.22 Transmit Command X Register (TXC1, TXC2, TXC3)
Each of the transmit endpoints (1, 3 and 5) has a Transmit Command register with the bits defined below.
TX_EN
Transmission Enable. This bit enables data transmission from the FIFO. It is cleared by the chip after transmitting a single
packet or after a STALL handshake in response to an IN token. It must be set by firmware to start packet transmission.
LAST
Setting this bit indicates that the entire packet has been written to the FIFO. This is used especially for streaming data to the
FIFO while the actual transmission occurs. If the LAST bit is not set and the transmit FIFO becomes empty during a trans-
mission, a stuff error followed by an EOP is forced on the bus. Zero length packets are indicated by setting this bit without
writing any data to the FIFO.
The transmit state machine transmits the payload data, CRC16 and the EOP signal before clearing this bit.
TOGGLE
The function of this bit differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset)
is used.
For non-ISO operation, it specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be gen-
erated, while a value of 1 causes a DATA1 PID to be generated.
For ISO operation, this bit and the LSB of the frame counter (FNL0) act as a mask for the TX_EN bit to allow pre-queueing
of packets to specific frame numbers; I.e. transmission is enabled only if bit 0 in the FNL register is set to TOGGLE. If an IN
token is not received while this condition is true, the contents of the FIFO are flushed with the next SOF. If the endpoint is
set to ISO, data is always transferred with a DATA0 PID.
This bit is not altered by hardware.
FLUSH
Writing a 1 to this bit flushes all data from the corresponding transmit FIFO, resets the endpoint to Idle state, and clears both
the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data is flushed after the transmission is
complete. After data flushing, this bit is reset by hardware.
RFF
Refill FIFO. Setting the LAST bit automatically saves the Transmit Read Pointer (TXRP) to a buffer. When the RFF bit is set,
the buffered TXRP is reloaded into the TXRP. This allows the user to repeat the last transaction if no ACK was received from
the host. If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After
reload, this bit is reset by hardware.
TFWL
Transmit FIFO Warning Limit. These bits specify how many more bytes can be transmitted from the respective FIFO before
an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit,
the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before
a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENx in the TXCx register
is set). See Table 8.
IGN_ISOMSK
bit 7
r/w
0
(Continued)
bit 6
TFWL1-0
0
r/w
bit 5
0
r/w HW
bit 4
RFF
0
47
FLUSH
r/w HW
bit 3
0
TOGGLE
bit 2
r/w
0
r/w HW
LAST
bit 1
0
r/w HW
TX_EN
bit 0
0
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