C500MP102EV3 Omron, C500MP102EV3 Datasheet - Page 54

• Manufacturer Part Number: C500MP102EV3
• Description: K-TYPE PC MEMORY RACK
• Manufacturer: Omron

Specifications of C500MP102EV3

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The Ladder Diagram
42
Interlocks
0000
0001
0002
0000
0001
0002
0003
0005
0006
Diagram B: Corrected with an Interlock
0004
The problem of storing execution conditions at branching points can also be
handled by using the INTERLOCK (IL(02)) and INTERLOCK CLEAR
(ILC(03)) instructions. The branching point and all the conditions leading to it
are placed on a separate line followed by all of the lines from the branching
point. Each branch line is thus established as an new instruction line, with the
first condition on each branch line corresponding to a LOAD or LOAD NOT
instruction. If the execution condition for the INTERLOCK instruction is OFF,
all instructions on the right side of the branch lines leading from the branch-
ing point receive an OFF execution condition through the first INTERLOCK
CLEAR instruction. The effect that this has on particular instructions is de-
scribed in 5-7 INTERLOCK and INTERLOCK CLEAR - IL(02) and ILC(03) .
Diagram B from the initial example can also be corrected with an interlock.
As shown below, this requires two more instruction lines for the interlock in-
structions.
If 0000 is ON in the revised version of diagram B, above, the status of 0001
and that of 0002 would determine the execution conditions for instructions 1
and 2, respectively, on independent instruction lines. Because here 0000 is
ON, this would produce the same results as ANDing the status of each of
these bits, as would occur if the interlock was not used, i.e., the INTERLOCK
and INTERLOCK CLEAR instructions would not affect execution. If 0000 is
OFF, the INTERLOCK instruction would produce an OFF execution condition
for instructions 1 and 2 and then execution would continue with the instruc-
tion line following the INTERLOCK CLEAR instruction.
As shown in the following diagram, more than one INTERLOCK instruction
can be used within one instruction block; each is effective through the next
INTERLOCK CLEAR instruction.
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 1
Instruction 2
ILC(03)
ILC(03)
IL(02)
IL(02)
IL(02)
Address Instruction
Address
0000
0001
0002
0003
0004
0005
0006
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
Instruction
LD
IL(02)
LD
Instruction 1
LD
Instruction 2
ILC(03)
LD
IL(02)
LD
Instruction 1
LD
IL(02)
LD
AND NOT
Instruction 2
LD
Instruction 3
LD
Instruction 4
ILC(03)
Operands
Operands
Section 4-3
0000
0001
0002
0000
0001
0002
0003
0004
0005
0006
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