C500MP102EV3 Omron, C500MP102EV3 Datasheet - Page 86

• Manufacturer Part Number: C500MP102EV3
• Description: K-TYPE PC MEMORY RACK
• Manufacturer: Omron

Specifications of C500MP102EV3

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit Control Instructions
5-6
5-6-1
5-6-2
OUTPUT – OUT
OUTPUT NOT –
OUT NOT
Limitations
Description
Flags
Bit Control Instructions
OUTPUT and OUTPUT NOT – OUT and OUT NOT
DIFFERENTIATE UP and DIFFERENTIATE DOWN –
DIFU(13) and DIFD(14)
There are five instructions that can be used generally to control individual bit
status. These are OUT, OUT NOT, DIFU(13), DIFD(14), and KEEP(11).
These instructions are used to turn bits ON and OFF in different ways.
Any output bit can be used in only one instruction that controls its status. See
3-3 Internal Relay (IR) Area for details.
OUT and OUT NOT are used to control the status of the designated bit ac-
cording to the execution condition.
OUT turns ON the designated bit for a ON execution condition, and turns
OFF the designated bit for an OFF execution condition. OUT with a TR bit
appears at a branching point rather than at the end of an instruction line.
OUT NOT turns ON the designated bit for a OFF execution condition, and
turns OFF the designated bit for an ON execution condition.
OUT and OUT NOT can be used to control execution by turning ON and OFF
bits that are assigned to conditions on the ladder diagram, thus determining
execution conditions for other instructions. This is particularly helpful when a
complex set of conditions can be used to control the status of a single work
bit, and then that work bit can be used to control other instructions.
The length of time that a bit is ON or OFF can be controlled by combining the
OUT or OUT NOT with TIM. Refer to Examples under 5-11-1 TIMER – TIM
for details.
There are no flags affected by these instructions.
Ladder Symbol
Ladder Symbol
Ladder Symbol
Ladder Symbol
DIFU(13) B
DIFD(14) B
B
B
Operand Data Areas
Operand Data Areas
Operand Data Areas
Operand Data Areas
IR, HR
IR, HR
B: Bit
B: Bit
IR, HR, TR
IR, HR, TR
B: Bit
B: Bit
Section 5-6
75