EVAL-ADF4106EBZ1 Analog Devices Inc, EVAL-ADF4106EBZ1 Datasheet - Page 14

• Manufacturer Part Number: EVAL-ADF4106EBZ1
• Description: ADF4106 Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4106EBZ1

• Silicon Manufacturer: Analog Devices
• Application Sub Type: PLL Frequency Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: ADF4106
• Kit Contents: Board Including Synthesizer, Cables
• Main Purpose: Timing, Frequency Synthesizer
• Embedded: No
• Utilized Ic / Part: ADF4106
• Primary Attributes: Single Integer-N PLL
• Secondary Attributes: 6GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4106
Table 9. Function Latch Map
PRESCALER
DB23
P2
0
0
1
1
P2
VALUE
DB22
P1
P1
0
1
0
1
CE PIN
0
1
1
1
DB21
PD2
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
CPI6
CPI6
CPI3
0
0
0
0
1
1
1
1
PRESCALER VALUE
8/9
16/17
32/33
64/65
CURRENT
SETTING
PD2
X
X
0
1
CPI5
2
CPI5
CPI2
0
0
1
1
0
0
1
1
CPI4
PD1
X
0
1
1
CPI3
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CURRENT
SETTING
CPI4
CPI1
0
1
0
1
0
1
0
1
CPI2
MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
1
CPI1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
4.24
5.30
6.36
7.42
8.50
3kΩ
1.06
2.12
3.18
TC4
TIMER COUNTER
TC3
5.1kΩ
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CONTROL
I
CP
(mA)
TC2
Rev. C | Page 14 of 24
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
11kΩ
0.289
0.580
0.870
1.160
1.450
1.730
2.020
2.320
TC1
F5
F4
0
1
1
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
DB9
F4
F5
X
0
1
F3
0
1
DB8
F3
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
F2
0
1
DB7
F2
M3
0
0
0
0
1
1
1
1
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
DB6
M3
CONTROL
MUXOUT
DB5
M2
M2
0
0
1
1
0
0
1
1
DB4
M1
DB3
PD1
0
M1
0
1
0
1
1
0
1
F1
0
1
DB2
F1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
DD
C2 (1) C1 (0)
DB1
CONTROL
BITS
DB0