EVAL-ADF4106EBZ1 Analog Devices Inc, EVAL-ADF4106EBZ1 Datasheet - Page 6

• Manufacturer Part Number: EVAL-ADF4106EBZ1
• Description: ADF4106 Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4106EBZ1

• Silicon Manufacturer: Analog Devices
• Application Sub Type: PLL Frequency Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: ADF4106
• Kit Contents: Board Including Synthesizer, Cables
• Main Purpose: Timing, Frequency Synthesizer
• Embedded: No
• Utilized Ic / Part: ADF4106
• Primary Attributes: Single Integer-N PLL
• Secondary Attributes: 6GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4106
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
LFCSP
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
CPGND
Figure 3. 16-Lead TSSOP Pin Configuration
AGND
RF
RF
REF
AV
R
SET
IN
IN
CP
DD
IN
B
A
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
CE
CLK
DATA
LE
MUXOUT
DV
V
EP
1
2
3
4
5
6
7
8
SET
P
IN
IN
DD
(Not to Scale)
DD
IN
ADF4106
B
A
TOP VIEW
Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R
So, with R
Charge Pump Output. When enabled, this provides ±I
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 18.
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ. See Figure 18. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device, depending on the status of the
power-down bit, F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.
This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches with the latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
Charge Pump Power Supply. This should be greater than or equal to V
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
Exposed Pad. The exposed pad must be connected to AGND.
16
15
14
13
12
11
10
9
I
CP
V
DV
MUXOUT
LE
DATA
CLK
CE
DGND
P
MAX
DD
SET
=
= 5.1 kΩ, I
R
25
SET
5 .
CP MAX
Rev. C | Page 6 of 24
= 5 mA.
SET
pin is 0.66 V. The relationship between I
Figure 4. 20-Lead LFCSP_VQ Pin Configuration
CPGND 1
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CP
AGND 2
AGND 3
RF
RF
CONNECTED TO AGND.
to the external loop filter, which in turn
IN
IN
DD
DD
B 4
A 5
must be the same value as DV
must be the same value as AV
ADF4106
TOP VIEW
PIN 1
INDICATOR
DD
/2 and a dc equivalent input
DD
. In systems where V
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
CP
and R
SET
DD
DD
is
.
.
DD
is 3 V,