EVAL-ADF4106EBZ1 Analog Devices Inc, EVAL-ADF4106EBZ1 Datasheet - Page 3

• Manufacturer Part Number: EVAL-ADF4106EBZ1
• Description: ADF4106 Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4106EBZ1

• Silicon Manufacturer: Analog Devices
• Application Sub Type: PLL Frequency Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: ADF4106
• Kit Contents: Board Including Synthesizer, Cables
• Main Purpose: Timing, Frequency Synthesizer
• Embedded: No
• Utilized Ic / Part: ADF4106
• Primary Attributes: Single Integer-N PLL
• Secondary Attributes: 6GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
AV
unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
REF
PHASE DETECTOR
CHARGE PUMP
LOGIC INPUTS
LOGIC OUTPUTS
POWER SUPPLIES
RF Input Frequency (RF
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency
REF
REF
REF
REF
Phase Detector Frequency
I
I
Sink and Source Current Matching
I
I
V
V
I
C
V
V
I
V
AV
DV
V
I
I
I
I
Power-Down Mode
CP
CP
CP
CP
INH
OH
DD
DD
DD
P
DD
IN
IH
IL
IN
OH
OH
OL
P
, Input Low Voltage
(AI
High Value
Low Value
Absolute Accuracy
R
, Input High Voltage
7
8
9
Sink/Source
Three-State Leakage
vs. V
vs. Temperature
, Input Capacitance
DD
CHARACTERISTICS
, I
DD
, Output Low Voltage
, Output High Voltage
, Output High Voltage
= DV
IN
IN
IN
IN
SET
(AI
(AI
(AI
INL
DD
Input Frequency
Input Sensitivity
Input Capacitance
Input Current
Range
, Input Current
DD
DD
DD
CP
+ DI
DD
+ DI
+ DI
+ DI
DD
= 3 V ± 10%, AV
DD
DD
DD
)
)
)
)
3
10
4
IN
)
6
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
B Version
0.5/6.0
–10/0
300
325
20/300
0.8/V
10
±100
104
5
625
2.5
3.0/11
2
2
1.5
2
1.4
0.6
±1
10
1.4
V
100
0.4
2.7/3.3
AV
AV
11
11.5
13
0.4
10
DD
DD
DD
− 0.4
/5.5
DD
1
B Chips
–10/0
300
325
20/300
0.8/V
±100
104
1.5
0.6
±1
1.4
V
100
0.4
AV
0.4
10
0.5/6.0
10
5
625
2.5
3.0/11
2
2
2
1.4
10
2.7/3.3
AV
9.0
9.5
10.5
DD
DD
DD
− 0.4
/5.5
DD
Rev. C | Page 3 of 24
2
(typ)
Unit
GHz min/max
dBm min/max
MHz max
MHz
MHz min/max
V p-p min/max
pF max
μA max
MHz max
mA typ
μA typ
% typ
kΩ typ
nA max
% typ
% typ
% typ
V min
V max
μA max
pF max
V min
V min
μA max
V max
V min/V max
V min/V max
mA max
mA max
mA max
mA max
μA typ
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
See Figure 18 for input circuit
Programmable, see Table 9
Test Conditions/Comments
For lower frequencies, ensure
slew rate (SR) > 320 V/μs
P = 8
P = 16
For f < 20 MHz, ensure SR > 50 V/μs
Biased at AV
ABP = 0, 0 (2.9 ns antibacklash pulse width)
With R
With R
See Table 9
1 nA typical; T
0.5 V ≤ V
0.5 V ≤ V
V
Open-drain output chosen, 1 kΩ pull-up
resistor to 1.8 V
CMOS output chosen
I
AV
9.0 mA typ
9.5 mA typ
10.5 mA typ
T
OL
A
CP
= 25°C
= 500 μA
DD
= V
≤ V
SET
SET
P
/2
CP
CP
P
= 5.1 kΩ
= 5.1 kΩ
≤ 5.5V
≤ V
≤ V
DD
A
P
P
/2 (see Note 5
= 25°C
− 0.5 V
− 0.5 V
5
)
A
= T
ADF4106
MAX
to T
MIN
,