HW-USB-IIG Xilinx Inc, HW-USB-IIG Datasheet - Page 27

• Manufacturer Part Number: HW-USB-IIG
• Description: IC CABLE
• Manufacturer: Xilinx Inc

Specifications of HW-USB-IIG

• Supply Voltage: 5.25V
• Accessory Type: Platform Cable USB II
• Ic Cable Type: Download Cable
• Connector Type B: USB A Plug
• Connector Type A: 2-mm Shrouded Keyed Socket
• Silicon Family Name: Virtex II, Spartan II
• Core Architecture: FPGA
• Core Sub-architecture: Virtex, Spartan, XC4000
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

X-Ref Target - Figure 28
Signal Integrity
Platform Cable USB II uses high-slew-rate buffers to drive its output pins. Each buffer has a 30.1Ω series termination
resistor. Users should pay close attention to PCB layout to avoid transmission line effects. Visit the
Central
If the target system has only one programmable device, the 2-mm connector should be located as close as possible to the
target device. If there are multiple devices in a JTAG or slave-serial single chain on the target system, users should consider
buffering TCK_CCLK_SCK. Differential driver/receiver pairs provide excellent signal quality when the rules identified in
Figure 29
X-Ref Target - Figure 29
Each differential driver and/or receiver pair contributes approximately 5 ns of propagation delay. This delay is insignificant
when using 12 MHz or slower clock speeds.
DS593 (v1.2.1) March 17, 2011
website, and see XAPP361, Planning for High Speed XC9500XV Designs for detailed signal integrity assistance.
are followed. Buffering is essential if target devices are distributed over a large PCB area.
Propagation delay from A to B (26 ns) captured directly at
the target represents 70% of the total propagation delay
seen by the cable (Figure 25).
TCK
TDO
Figure 28: TDO Sampling Example at 12 MHz (Analog Signals on Target System)
TCK_CCLK_SCK
Figure 29: Differential Clock Buffer Example
Four Differential
SN65LVDS105
Drivers
1
4
Locate driver package adjacent to 2-mm connector
TDO Sampling Point
www.xilinx.com
SN65LVDS2 (2)
pair in parallel with equal length and
consistent spacing
Route A & B traces for each differential
Locate one receiver adacent
to each target device
TDO Sampling Point
TCK_CCLK_SCK1
TCK_CCLK_SCK4
Series Termination Resistor
(20Ω −30Ω)
DS593_29_021408
Four
Buffered
Clocks
DS593_28_021408
Xilinx Signal Integrity
Platform Cable USB II
27