STA308HB-EVB STMicroelectronics, STA308HB-EVB Datasheet
STA308HB-EVB
Specifications of STA308HB-EVB
Related parts for STA308HB-EVB
STA308HB-EVB Summary of contents
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MULTICHANNEL DIGITAL AUDIO PROCESSOR WITH DDX™ 8 DDX TM Channels Capability (24 bit) From 32kHz to 192kHz Input Sample Rates Supported Volume Control from 0 to -127 dB (0.5 dB steps) Variable Digital Gain from 0 to 24dB (0.5dB steps) ...
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STA308 BLOCK DIAGRAM LRCKI BICKI SERIAL SDI12 DATA SDI34 IN SDI56 SDI78 CHANNEL MAPPING SYSTEM TIMING PLLB PLL XTI CKOUT Figure 1. Signal Flow Diagram Channels 1-8 1st Stage Interpolation Output 8 Inputs From I2S Channel Mapping 2/33 SA SCL ...
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IN CONNECTION (Top view) MVO GND VDD3 GND VDD SDI_78 SDI_56 SDI_34 SDI_12 LRCKI BICKI VDD3 GND VDD RESET PLLB PIN FUNCTION PIN NAME 1 MVO 3, 12, 24, 28, VDD3 35, 44, 52 13, 27, GND ...
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STA308 PIN FUNCTION (continued) PIN NAME 20 XTI 21 FILTER_PLL 22 VDDA 23 GNDA 25 CKOUT 29 OUT8_B 30 OUT8_A 31 OUT7_B 32 OUT7_A 33 OUT6_B 34 OUT6_A 38 OUT5_B 39 OUT5_A 40 OUT4_B 41 OUT4_A 42 OUT3_B 43 OUT3_A ...
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ABSOLUTE MAXIMUM RATINGS Symbol V 3.3V I/O Power Supply DD_3.3 V 2.5V Logic Power Supply DD_2.5 V Voltage on input pins i V Voltage on output pins o T Storage Temperature stg T Ambient Operating Temperature amb THERMAL DATA Symbol ...
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STA308 ELECTRICAL CHARACTERISTCS (V wise specified) GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input no pull- High Level Input no pull-down ih I Tristate output leakage without OZ pullup/down V Electrostatic Protection esd Note 1: The ...
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PIN DESCRIPRTION 1.1 MVO: Master Volume Override This pin enables the user to bypass the Volume Control on all channels. When MVO is pulled High, the Master Volume Register is set to 00h, which corresponds to its Full Scale ...
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STA308 2.1 COMMUNICATION PROTOCOL 2.1.1 Data Transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. ...
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Write Mode Sequence BYTE DEV-ADDR WRITE START MULTIBYTE DEV-ADDR WRITE START Read Mode Sequence ACK CURRENT DEV-ADDR ADDRESS READ START RW ACK RANDOM DEV-ADDR ADDRESS READ START RW RW= ACK HIGH SEQUENTIAL DEV-ADDR CURRENT READ START ACK SEQUENTIAL DEV-ADDR RANDOM ...
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STA308 10h C8Vol C8V7 11h C12im 12h C34im 13h C56im 14h C78im 15h C1234ls C4LS1 16h C5678ls C8LS1 17h L1ar L1R3 18h L1atrt L1AT3 19h L2ar L2R3 1Ah L2atrt L2AT3 1Bh Tone TTC3 1Ch Cfaddr CFA7 1Dh B2cf1 C1B23 1Eh ...
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CONFIGURATION REGISTER A (ADDRESS 00H) BIT D7 D6 NAME MPC HPE RST 1 3.0.1 Master Clock Select BIT R/W RST R/W 0 The STA308 will support sample rates of 32kHz, 44.1kHz, 48Khz, ...
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STA308 3.0.3 Bass Management Enable BIT R/W RST NAME 5 R/W 0 BME Channel 6 of the STA308 features a bass management mode that enables redirection of information in all other channels to this channel and which can then be ...
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Serial Audio Input Interface Format BIT R/W RST R/W 0 The STA308 features a configurable digital serial audio interface. The settings of the SAIx bits determine how the input to this interface is ...
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STA308 3.1.3 Serial Audio Input Interface First Bit BIT R/W RST NAME 5 R/W 0 SAIFB 3.1.4 Zero-Crossing Volume Enable BIT R/W RST NAME 6 R/W 1 ZCE The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on ...
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High-Pass Filter Bypass BIT R/W RST 7 R/W 0 The STA308 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. ...
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STA308 3.3.4 Biquad Coefficient Link BIT R/W RST NAME 7 R/W 0 BQL For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM space by setting the BQL bit to 1. Then ...
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Table 4. Interface format as a function of SAO bits. SAO(2..0) Interface Format 000 001 Left-Justified Data 010 Right-Justified 16-bit Data 011 Right-Justified 18-bit Data 100 Right-Justified 20-bit Data 101 Right-Justified 24-bit Data BIT R/W RST 6 ...
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STA308 3.7 Master Volume Register (address 07h) BIT D7 D6 NAME MV7 MV6 RST 1 3.8 Channels 1,2,3,4,5,6,7,8 Mute (address 08h) BIT D7 D6 NAME C8M C7M RST 0 3.9 Channel 1 Volume (address 09h) BIT D7 D6 NAME C1V7 ...
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Channel 6 Volume (address 0Eh) BIT D7 D6 NAME C6V7 C6V6 RST 0 3.15 Channel 7 Volume (address 0Fh) BIT D7 D6 NAME C7V7 C7V6 RST 0 3.16 Channel 8 Volume (address 10h) BIT D7 D6 NAME C8V7 C8V6 ...
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STA308 Channel Volume as a function of CxV(7..0) CxV(7..0) 00000000(00h) 00000001(01h) 00000010(02h) … 00101111(2Fh) 00110000(30h) 00110001(31h) … 11111110(FEh) 11111111(FFh) 3.17 Channel Input Mapping Channels 1 & 2 (address 11h) BIT D7 D6 NAME C2IM2 RST 3.18 Channel Input Mapping Channels ...
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Table 6. Channel Mapping as a function of CxIM bits 2 CxIM(2.. Input Mapped to: 000 Channel 1 001 Channel 2 010 Channel 3 011 Channel 4 100 Channel 5 101 Channel 6 110 Channel 7 111 Channel ...
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STA308 3.23 Limiter 1 Attack/Release Rate (address 17h) BIT D7 D6 NAME L1R3 L1R2 RST 1 3.24 Limiter 1 Attack/Release Threshold (address 18h) BIT D7 D6 NAME L1AT3 L1AT2 RST 0 3.25 Limiter 2 Attack/Release Rate (address 19h) BIT D7 ...
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The limiter attack thresholds are determined by the LxAT registers recommended in ...
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STA308 Table 9. Limiter Release Rate and Uncompression Threshold as a function of LxR bits LxR(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 10. Limiter Attack Threshold as a function ...
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Table 11. Limiter Release Threshold as a function of LxRT bits LxRT(3..0) AC(dB relative to FS) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 3.27 Bass and Treble Tone Control(address 1Bh) BIT ...
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STA308 3.28 Coefficient Address Register (address 1Ch) BIT D7 D6 NAME CFA7 CFA6 RST 0 3.29 Coefficient b2 Data Register Bits 23..16 (address 1Dh) BIT D7 D6 NAME C1B23 C1B22 RST 0 3.30 Coefficient b2 Data Register Bits 15..8 (address ...
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Coefficient a2 Data Register Bits 15..8 (address 24h) BIT D7 D6 NAME C3B15 C3B14 RST 0 3.37 Coefficient a2 Data Register Bits 7..0 (address 25h) BIT D7 D6 NAME C3B7 C3B6 RST 0 3.38 Coefficient a1 Data Register Bits ...
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STA308 3.44 Coefficient Write Control Register (address 2Ch) BIT D7 D6 NAME RST Coefficients for EQ and Bass Management are handled internally in the STA308 via RAM. Access to this RAM is available to the user via an I2C register ...
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When using this technique, the 8-bit address would specify the address of the biquad b2 coefficient (e. 10, 15, …, 50, … 195 decimal), ...
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STA308 Post-Scale The STA308 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiply. The scale factor for this multiply is loaded into RAM using the ...
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DIM. MIN. TYP. MAX. MIN. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.17 0.22 0.27 0.0066 0.0086 0.0106 C 0.09 0.0035 D 11.80 12.00 12.20 0.464 D1 9.80 10.00 10.20 0.386 D3 7.50 e ...
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STA308 4.0 REVISION HISTORY Table 13. Revision History Date Revision April 2004 30-Apr-2010 32/33 2 Updates not recorded 3 Removed "Preliminary data" status from cover page Description of Changes ...
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