STA013EVB STMicroelectronics, STA013EVB Datasheet
STA013EVB
Specifications of STA013EVB
Related parts for STA013EVB
STA013EVB Summary of contents
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SINGLE CHIP MPEG2 LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) - All features specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) - Lower sampling frequencies syntax extension, ...
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STA013 - STA013B - STA013T Figure 1. Block Diagram: MPEG 2.5 Layer III Decoder Hardware Partitioning. RESET 26 5 SDI SERIAL 6 SCKR BUFFER INPUT INTERFACE 7 BIT_EN 8 SRC_INT OUT_CLK/DATA_REQ THERMAL DATA Symbol R Thermal resistance Junction to Ambient ...
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Figure 2. Pin Connection SRC_INT N.C. LRCKT OCLK N.C. VSS_2 VDD_2 VSS_3 VDD_3 N.C. PVDD PVSS VDD_1 1 28 OUT_CLK/DATA_REQ VSS_1 2 27 VSS_5 SDA 3 26 RESET ...
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STA013 - STA013B - STA013T PIN DESCRIPTION SO28 TQFP44 LFBGA64 ...
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ELECTRICAL CHARACTERISTICS: V specified DC OPERATING CONDITIONS Symbol V Power Supply Voltage DD GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input Current IL Without pull-up device I High Level Input Current IH Without pull-up device V Electrostatic ...
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... SCANEN Test Load V DD Output SDA Other Outputs V REF D98AU967 Other frequencies may be supported upon re- quest to STMicroelectronics. Each frequency is supported by downloading a specific configura- tion file, provided by STM XTI is an input Pad with specific levels. Test Condition SDA 3 SCL 4 SDO 9 SCKT 10 LRCKT 11 ...
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Figure 5. MPEG Decoder Interfaces. DATA_REQ SDI DATA SCKR SOURCE BIT_EN D98AU912 Figure 6. Serial Input Interface Clocks SDI SCKR SCKR BIT_EN 2.2 - Serial Input Interface STA013 receives the input data (MSB first) thought the Serial Input Interface (Fig.5). ...
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STA013 - STA013B - STA013T Figure 7. PLL and Clocks Generation System XTI 2.4 - PCM Output Interface The decoded audio data are output in serial PCM format. The interface consists of the following sig- nals: SDO PCM Serial Data ...
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STA013 Operation Mode The STA013 can work in two different modes, called Multimedia Mode and Broadcast Mode. In Multimedia Mode, STA013 decodes the in- coming bitstream, acting as a master of the data communication from the source to ...
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STA013 - STA013B - STA013T 3.1.2 - Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition termi- nates communications ...
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READ OPERATION (see Fig. 11) 3.4.1 - Current byte address read The STA013 has an internal byte address counter. Each time a byte is written or read, this counter is incremented. For the current byte address read mode, ...
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STA013 - STA013B - STA013T REGISTERS (continued) HEX_COD DEC_COD $43 67 HEAD_H[23:16] $44 68 HEAD_M[15:8] $45 69 HEAD_L[7:0] $46 70 DLA $47 71 DLB $48 72 DRA $49 73 DRB $50 80 MFSDF_441 $51 81 PLLFRAC_441_L $52 ...
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STA013 REGISTERS DESCRIPTION The STA013 device includes 128 I this document, only the user-oriented registers are described. The undocumented registers are reserved. These registers must never be ac- cessed (in Read or in Write mode). The Read- Only ...
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STA013 - STA013B - STA013T Hardware Reset: 0x01 The REQ_POL registers is used to program the polarity of the DATA_REQ line. MSB Default polarity (the source sends data when the ...
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MUTE Address: 0x14 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB don’t care normal operation mute The MUTE command is handled according to ...
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STA013 - STA013B - STA013T ANCCOUNT_L Address: 0x41 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB AC7 AC6 AC5 AC4 AC3 ANCCOUNT_H Address: 0x42 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_H MSB ...
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The meaning of the flags are shown in the follow- ing tables: MPEG IDs IDex Layer in Layer III these two flags must be set always to "01". Protection_bit It equals ...
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STA013 - STA013B - STA013T DLA Address: 0x46 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB DLA7 DLA6 DLA5 DLA4 DLA ...
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DRA Address: 0x48 Type: R/W Software Reset: 0X00 Hardware Reset: 0X00 MSB DRA7 DRA6 DRA5 DRA4 DRA register is used to attenuate ...
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STA013 - STA013B - STA013T PLLFRAC_441_H Address: 0x52 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB PF15 PF14 PF13 PF12 PF11 PF10 PF9 The registers are considered logically concate- nated and contain the fractional ...
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PCMCONF Address: 0x55 Type: R/W Software Reset: 0x21 Hardware Reset: 0x21 MSB ORD DIF INV ...
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STA013 - STA013B - STA013T PCMCROSS Address: 0x56 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB The default configuration ...
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PLLFRAC_L ([7:0]) MSB PF7 PF6 PF5 PF4 PF3 PLLFRAC_H ([15:8]) MSB PF15 PF14 PF13 PF12 PF11 PF10 PF9 Address: 0x64 - 0x65 Type: R/W Software Reset: 0x46 | 0x5B Hardware ...
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STA013 - STA013B - STA013T RUN Address: 0x72 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB Setting this register to 1, STA013 leaves the idle state, starting the decoding ...
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TREBLE_ENHANCE Address: 0x7B Software Reset: 0x00 Hardware Reset: 0x00 MSB TE7 TE6 TE5 TE4 TE3 MSB ...
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STA013 - STA013B - STA013T BASS_ENHANCE Address: 0x7C Software Reset: 0x00 Hardware Reset: 0x00 MSB BE7 BE6 BE5 BE4 BE3 MSB ...
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TONE_ATTEN Address: 0x7D Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB TA7 TA6 TA5 TA4 TA3 MSB ...
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STA013 - STA013B - STA013T The Ancillary Data extraction on STA013 can be described as follow: STA013 has a specific Ancillary Data buffer, mapped into the I2C registers: 0x59 ANC_DATA_1 0x5A ANC_DATA_2 0x5B ANC_DATA_3 0x5C ANC_DATA_4 0x5D ANC_DATA_5 Since the ...
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TIMING DIAGRAMS 5.4.1. Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC OCLK (OUTPUT) SDO SCKT LRCLK tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing ...
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STA013 - STA013B - STA013T 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0 BIT_EN SCKR SDI 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1 BIT_EN SCKR SDI tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns ...
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RESET The Reset min duration (t_reset_low_min) is 100ns RESET 5.5. CONFIGURATION FLOW HW RESET set PCM-DIVIDER set PCM-CONF. set { PLL FRAC_441_H, PLL FRAC_441_L, PLL FRAC_H, PLL FRAC_L } set { MFS DF_441, MFSDF } set PLL CTRL set ...
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STA013 - STA013B - STA013T Table 5: PLL Configuration Sequence For 10MHz Input Clock 256 Oversapling Clock REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table ...
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Table 9: PLL Configuration Sequence For 14.31818MHz Input Clock 512 Oversapling Rathio REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table 10: PLL Configuration Sequence For ...
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STA013 - STA013B - STA013T 5.6. STA013 CONFIGURATION FILE FORMAT The STA013 Configuration File is an ASCII format. An example of the file format is the following 128 15 ............ sequence of rows ...
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DIM. MIN. TYP. MAX. MIN. A 2.65 a1 0.1 0.3 0.004 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0 (typ.) D 17.7 18.1 0.697 E 10 10.65 0.394 e 1.27 e3 16.51 F 7.4 7.6 ...
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STA013 - STA013B - STA013T mm DIM. MIN. TYP. MAX. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.30 0.37 0.45 0.012 C 0.09 0.20 0.004 D 11.80 12.00 12.20 0.464 D1 9.80 10.00 10.20 0.386 ...
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DIM. MIN. TYP. MAX. MIN. A 1.700 A1 0.350 0.400 0.450 0.014 A2 1.100 b 0.500 D 8.000 D1 5.600 e 0.800 E 8.000 E1 5.600 f 1.200 BALL 1 IDENTIFICATION ...
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