OM13005,598 NXP Semiconductors, OM13005,598 Datasheet
OM13005,598
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EM773 Energy metering IC flash and 8 kB SRAM Rev. 1 — 1 September 2010 1. General description The EM773 is an ARM Cortex-M0 based, low-cost 32-bit energy metering IC, designed for 8/16-bit smart metering applications. ...
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... NXP Semiconductors Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. One SPI controller with SSP features and with FIFO and multi-protocol capabilities C-bus interface supporting full I data rate of 1 Mbit/s with multiple address recognition and monitor mode. ...
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... NXP Semiconductors 5. Block diagram EM773 system bus slave HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD UART DTR, CTS, RTS CT32B0_MAT[2:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 Fig 1. EM773 block diagram EM773 Objective data sheet SWD IRC TEST/DEBUG ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning terminal 1 index area PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 XTALOUT PIO0_2/SSEL0/CT16B0_CAP0 Fig 2. Pin configuration HVQFN 33 package EM773 Objective data sheet XTALIN PIO1_8 Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 September 2010 EM773 ...
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... NXP Semiconductors 6.2 Pin description Table 2. EM773 pin description table (HVQFN33 package) Symbol Pin PIO0_0 to PIO0_10 [2] RESET/PIO0_0 2 [3] PIO0_1/CLKOUT/ 3 CT32B0_MAT2 [3] PIO0_2/SSEL0/ 8 CT16B0_CAP0 [3] PIO0_3 9 [4] PIO0_4/SCL 10 [4] PIO0_5/SDA 11 [3] PIO0_6/SCK0 15 [3] PIO0_7/CTS 16 [3] PIO0_8/MISO0/ 17 CT16B0_MAT0 [3] PIO0_9/MOSI0/ 18 CT16B0_MAT1 EM773 Objective data sheet Start ...
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... NXP Semiconductors Table 2. EM773 pin description table (HVQFN33 package) Symbol Pin [3] SWCLK/PIO0_10/SCK0/ 19 CT16B0_MAT2 [5] I_HIGHGAIN 21 PIO1_1 to PIO1_9; PIO1_11 [5] VOLTAGE 22 [5] R/PIO1_1/ 23 CT32B1_MAT0 [5] R/PIO1_2/ 24 CT32B1_MAT1 [5] SWDIO/PIO1_3/ 25 CT32B1_MAT2 PIO1_4/ 26 CT32B1_MAT3/WAKEUP [3] PIO1_5/RTS/ 30 CT32B0_CAP0 [3] PIO1_6/RXD/ 31 CT32B0_MAT0 [3] PIO1_7/TXD/ 32 CT32B0_MAT1 [3] PIO1_8 7 [3] PIO1_9 12 I_LOWGAIN 20 EM773 Objective data sheet … ...
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... NXP Semiconductors Table 2. EM773 pin description table (HVQFN33 package) Symbol Pin PIO1_11 27 PIO2_0 [3] PIO2_0/DTR 1 PIO3_0 to PIO3_5 [3] PIO3_2 28 [3] PIO3_4 13 [3] PIO3_5 [6] XTALIN 4 [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled. [2] See Figure 24 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...
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... NXP Semiconductors 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The EM773 contains on-chip flash memory. 7.3 On-chip SRAM The EM773 contains a total on-chip static RAM memory. ...
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... NXP Semiconductors EM773 4 GB reserved AHB peripherals reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM reserved 32 kB on-chip flash 0 GB Fig 3. EM773 memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts ...
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... NXP Semiconductors • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source ...
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... NXP Semiconductors The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.8.1 Features • Maximum UART data bit rate of 3.125 MBit/s. • 16 Byte Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. ...
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... NXP Semiconductors 7.10.1 Features • 2 The C-bus interface also supports Fast-mode Plus with bit rates Mbit/s. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). ...
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... NXP Semiconductors • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • four external outputs corresponding to match registers, with the following capabilities: – ...
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... NXP Semiconductors Following reset, the EM773 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 4 IRC oscillator watchdog oscillator MAINCLKSEL (main clock select) ...
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... NXP Semiconductors 7.15.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is ± ...
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... NXP Semiconductors 7.15.5.2 Deep-sleep mode In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down exception, the user has the option to keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows for additional power savings ...
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... NXP Semiconductors 7.16.4 Code security (Code Read Protection - CRP) This feature of the EM773 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location ...
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... NXP Semiconductors 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and external rail input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...
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... NXP Semiconductors 9. Static characteristics Table 4. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (core DD and external rail) I supply current DD Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage ...
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... NXP Semiconductors Table 4. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu High-drive output pin (PIO0_7) ...
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... NXP Semiconductors Table 4. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter I LOW-level output OL current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage ...
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... NXP Semiconductors Table 4. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Oscillator pins V crystal input voltage i(xtal) V crystal output voltage o(xtal) Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. ...
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... NXP Semiconductors 9.1 BOD static characteristics Table 5. ° amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see EM773 user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see EM773 user manual): • ...
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... NXP Semiconductors (mA) Conditions: T peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 5. Active mode: Typical supply current I ...
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... NXP Semiconductors I DD (mA) Conditions: V AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 7. Sleep mode: Typical supply current I clock frequencies ...
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... NXP Semiconductors 0 (μA) 0.6 0.4 0.2 Fig 9. Deep power-down mode: Typical supply current I different supply voltages V 9.3 Electrical pin characteristics 3 (V) 3.2 2.8 2.4 Conditions: V Fig 10. High-drive output: Typical HIGH-level output voltage V output current I EM773 Objective data sheet 0 −40 − °C 25 ° ...
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... NXP Semiconductors (mA Conditions: V Fig 11. I LOW-level output voltage (mA) 10 Conditions: V Fig 12. Typical LOW-level output current I EM773 Objective data sheet 0 0 0 pins PIO0_4 and PIO0_5 C-bus pins (high current sink): Typical LOW-level output current 0.2 = 3.3 V; standard port pins and PIO0_7. ...
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... NXP Semiconductors 3 (V) 3.2 2.8 2.4 Conditions: V Fig 13. Typical HIGH-level output voltage (μA) −10 −30 −50 −70 Conditions: V Fig 14. Typical pull-up current I EM773 Objective data sheet °C 25 °C −40 ° 3.3 V; standard port pins °C 25 °C −40 ° 3.3 V; standard port pins. ...
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... NXP Semiconductors (μ Conditions: V Fig 15. Typical pull-down current I EM773 Objective data sheet °C 25 °C −40 ° 3.3 V; standard port pins. DD versus input voltage V pd All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 September 2010 EM773 Energy metering IC 002aae989 ( © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Flash memory Table 6. − amb Symbol N endu t ret prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 10.2 External clock Table 7. ...
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... NXP Semiconductors 10.3 Internal oscillators Table 8. − amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply [2] voltages. 12.15 f (MHz) 12.05 11.95 11.85 Conditions: Frequency values are typical values. 12 MHz ± accuracy is guaranteed for 2.7 V ≤ ...
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... NXP Semiconductors 10.4 I/O pins Table 10. − amb Symbol [1] Applies to standard port pins and RESET pin. 2 10.5 I C-bus Table 11. − amb Symbol f SCL LOW t HIGH t HD;DAT t SU;DAT [1] See the I [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge ...
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... NXP Semiconductors [6] The maximum t output stage t SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. ...
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... NXP Semiconductors Table 12. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions t data set-up time in SPI mode DS t data hold time in SPI mode DH t data output valid time in SPI mode v(Q) t data output hold time in SPI mode h(Q) = (SSPCLKDIV × SCR) × CPSDVSR ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 20. SPI slave timing in SPI mode EM773 Objective data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t DS MOSI ...
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... NXP Semiconductors 11. Application information 11.1 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional ...
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... NXP Semiconductors Fig 22. Oscillator modes and models: oscillation mode of operation and external crystal model used for C Table 13. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 14. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 11.2 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip ...
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... NXP Semiconductors order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. 11.3 Standard I/O pad configuration Figure 23 • Digital output driver • Digital input: Pull-up enabled/disabled • ...
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... NXP Semiconductors 11.4 Reset pad configuration reset Fig 24. Reset pad configuration EM773 Objective data sheet GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 September 2010 EM773 Energy metering ESD PIN ESD V SS 002aaf274 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 7.1 mm nom 0.85 0.02 0.28 0.2 7.0 min 0.80 0.00 0.23 6 ...
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... NXP Semiconductors 13. Abbreviations Table 15. Acronym AHB AMBA APB BOD GPIO PLL RC SPI SSI SSP TTL UART EM773 Objective data sheet Abbreviations Description Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection General Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Serial Peripheral Interface ...
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... NXP Semiconductors 14. Revision history Table 16. Revision history Document ID Release date EM773 v.1 <tbd> EM773 Objective data sheet Data sheet status Change notice Objective data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 September 2010 EM773 Energy metering IC Supersedes - © ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Objective data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 8 7.1 ARM Cortex-M0 processor . . . . . . . . . . . . . . . . 8 7.2 On-chip flash program memory . . . . . . . . . . . . 8 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.4 Memory map ...