EFM32-TG-STK3300 Energy Micro, EFM32-TG-STK3300 Datasheet - Page 63

• Manufacturer Part Number: EFM32-TG-STK3300
• Description: MCU, MPU & DSP Development Tools TG Starter Kit
• Manufacturer: Energy Micro
• Series: EFM®32r
• Type: MCUr

Specifications of EFM32-TG-STK3300

• Processor To Be Evaluated: EFM32
• Processor Series: EMF32 Tiny Gecko
• Data Bus Width: 32 bit
• Interface Type: USB, JTAG, LCD, Touch Interface
• Operating Supply Voltage: 5 V
• Contents: Board, Cable, CD and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: EFM32-TGXXX

3.5.6.2 Operation
3.5.6.3 Restrictions
3.5.6.4 Condition flags
2011-02-04 - d0002_Rev1.00
where:
S
cond
Rd
Operand2 is a flexible second operand. See Section 3.3.3 (p. 38) for details of the options.
imm16
The MOV instruction copies the value of Operand2 into Rd.
When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax
is the corresponding shift instruction:
• ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
• LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n != 0
• LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
• ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
• RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:
• MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
• MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
• MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
• MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs
See Section 3.5.3 (p. 60) .
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value,
and places the result into Rd.
Note
You can use SP and PC only in the MOV instruction, with the following restrictions:
• the second operand must be a register without shift
• you must not specify the S suffix.
When Rd is PC in a MOV instruction:
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
Note
If S is specified, these instructions:
The MOVW instruction provides the same function as MOV, but is restricted to using the
imm16 operand.
Though it is possible to use MOV as a branch instruction, ARM strongly recommends the
use of a BX or BLX instruction to branch for software portability to the ARM instruction set.
is an optional suffix. If S is specified, the condition code flags are updated on the result of
the operation, see Section 3.3.7 (p. 43) .
is an optional condition code, see Section 3.3.7 (p. 43) .
is the destination register.
is any value in the range 0-65535.
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