EFM32-TG-STK3300 Energy Micro, EFM32-TG-STK3300 Datasheet - Page 96

• Manufacturer Part Number: EFM32-TG-STK3300
• Description: MCU, MPU & DSP Development Tools TG Starter Kit
• Manufacturer: Energy Micro
• Series: EFM®32r
• Type: MCUr

Specifications of EFM32-TG-STK3300

• Processor To Be Evaluated: EFM32
• Processor Series: EMF32 Tiny Gecko
• Data Bus Width: 32 bit
• Interface Type: USB, JTAG, LCD, Touch Interface
• Operating Supply Voltage: 5 V
• Contents: Board, Cable, CD and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: EFM32-TGXXX

4.3.2.1 About IT folding
4.3.3 CPUID Base Register
4.3.4 Interrupt Control and State Register
2011-02-04 - d0002_Rev1.00
In some situations, the processor can start executing the first instruction in an IT block while it is still
executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT
folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing
the task, to disable IT folding.
The CPUID register contains the processor part number, version, and implementation information. See
the register summary in Table 4.12 (p. 94) for its attributes. The bit assignments are:
Table 4.14. CPUID register bit assignments
The ICSR:
• provides:
• indicates:
31
Bits
[2]
[1]
[0]
Bits
[31:24]
[23:20]
[19:16]
[15:4]
[3:0]
• a set-pending bit for the Non-Maskable Interrupt (NMI) exception
• set-pending and clear-pending bits for the PendSV and SysTick exceptions
• the exception number of the exception being processed
• whether there are preempted active exceptions
• the exception number of the highest priority pending exception
• whether any interrupts are pending.
Im plem enter
Name
DISFOLD
DISDEFWBUF
DISMCYCINT
Name
Implementer
Variant
Constant
PartNo
Revision
24 23
Function
When set to 1, disables IT folding. see Section 4.3.2.1 (p. 96) for more information.
When set to 1, disables write buffer use during default memory map accesses. This causes
all bus faults to be precise bus faults but decreases performance because any store to
memory must complete before the processor can execute the next instruction.
Note
When set to 1, disables interruption of load multiple and store multiple instructions. This
increases the interrupt latency of the processor because any LDM or STM must complete
before the processor can stack the current state and enter the interrupt handler.
Function
Implementer code:
0x41 = ARM
Variant number, the r value in the rnpn product revision identifier:
0x2 = r2pX
Reads as 0xF
Part number of the processor:
0xC23 = Cortex-M3
Revision number, the p value in the rnpn product revision identifier:
0x0 = rXp0
0x1 = rXp1
Variant
This bit only affects write buffers implemented in the Cortex-M3 processor.
20 19
Constant
16 15
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96
PartNo
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4 3
Revision
0