5M1270ZT144C5N

Manufacturer Part Number5M1270ZT144C5N
DescriptionALTERA
ManufacturerAltera
SeriesMAX® V
5M1270ZT144C5N datasheets
 

Specifications of 5M1270ZT144C5N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max6.2ns
Voltage Supply - Internal1.71 V ~ 1.89 VNumber Of Logic Elements/blocks1270
Number Of Macrocells980Number Of Gates-
Number Of I /o114Operating Temperature0°C ~ 85°C
Mounting TypeSurface MountPackage / Case144-LQFP
Lead Free Status / Rohs StatusVendor undefined / RoHS Compliant  
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January 2011
MV51003-1.1
MV51003-1.1
This chapter covers the electrical and switching characteristics for MAX
Electrical characteristics include operating conditions and power consumptions. This
chapter also describes the timing model and specifications.
You must consider the recommended DC and switching conditions described in this
chapter to maintain the highest possible performance and reliability of the MAX V
devices.
This chapter contains the following sections:
“Operating Conditions” on page 3–1
“Power Consumption” on page 3–9
“Timing Model and Specifications” on page 3–10
Operating Conditions
Table 3–1
through
ratings, recommended operating conditions, DC electrical characteristics, and other
specifications for MAX V devices.
Absolute Maximum Ratings
Table 3–1
lists the absolute maximum ratings for the MAX V device family.
Table 3–1. Absolute Maximum Ratings for MAX V Devices
Symbol
Parameter
V
Internal supply voltage
CCINT
V
I/O supply voltage
CCIO
V
DC input voltage
I
I
DC output current, per pin
OUT
T
Storage temperature
STG
T
Ambient temperature
AMB
T
Junction temperature
J
Notes to
Table
3–1:
(1) For more information, refer to the
Operating Requirements for Altera Devices Data
(2) Conditions beyond those listed in
Table 3–1
ratings for extended periods of time may have adverse affects on the device.
(3) For more information about “under bias” conditions, refer to
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
MAX V Device Handbook
January 2011
3. DC and Switching Characteristics for
Table 3–15 on page 3–9
list information about absolute maximum
(Note
1),
(2)
Conditions
Minimum
With respect to ground
No bias
Under bias
(3)
TQFP and BGA packages
under bias
Sheet.
may cause permanent damage to a device. Additionally, device operation at the absolute maximum
Table
3–2.
MAX V Devices
®
V devices.
Maximum
Unit
–0.5
2.4
V
–0.5
4.6
V
–0.5
4.6
V
–25
25
mA
–65
150
°C
–65
135
°C
135
°C
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5M1270ZT144C5N Summary of contents

  • Page 1

    ... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

  • Page 2

    ... MAX V device ISP and/or user flash memory (UFM) programming using JTAG or logic array is not guaranteed outside the recommended operating conditions (for example, if brown-out occurs in the system during a potential write/program sequence to the UFM, Altera recommends that you read back the UFM contents and verify it against the intended write data). ...

  • Page 3

    ... Hysteresis for Schmitt V (8) SCHMITT trigger input (9) V supply current CCINT I CCPOWERUP during power-up (10) Value of I/O pin pull-up R resistor during user PULLUP mode and ISP January 2011 Altera Corporation (Note 1) (Part Conditions Minimum = V max (2) –10 I CCIO max (2) –10 O CCIO 5M40Z, 5M80Z, 5M160Z, and 5M240Z (Commercial grade) — ...

  • Page 4

    ... Conditions Minimum — — — — — — = 1.2, 1.5, 1.8, 2.5, or 3.3 V. CCIO time. CONFIG . CCIO Operating Conditions Typical Maximum Unit — 300 µA — — settings (3.3, 2.5, 1.8, 1.5, CCIO typical value is 300 mV SCHMITT January 2011 Altera Corporation ...

  • Page 5

    ... High-level output voltage OH V Low-level output voltage OL Note to Table 3–5: (1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the MAX V Device Architecture chapter. January 2011 Altera Corporation (Note 1) MAX V Output Drive 0.0 0.5 2 ...

  • Page 6

    ... V IH Operating Conditions Maximum Unit 3.6 V 4.0 V 0.8 V — V 0.2 V Maximum Unit 2.625 V 4.0 V 0.7 V — V — V — V 0.2 V 0.4 V 0.7 V Maximum Unit 1.89 V 2.25 (2) V 0.35 × CCIO — V 0.45 V parameter I January 2011 Altera Corporation ...

  • Page 7

    ... I/O supply voltage CCIO V Differential output voltage swing OD V Output offset voltage OS Note to Table 3–12: (1) Supports emulated LVDS output using a three-resistor network (LVDS_E_3R). January 2011 Altera Corporation Conditions Minimum — 1.425 — 0.65 × V CCIO — –0.3 IOH = –2 mA (1) 0.75 × V ...

  • Page 8

    ... Operating Conditions Typical Maximum Unit 2.5 2.625 V — 600 mV 1.25 1.375 V 2.5 V 3.3 V Unit Min Max Min Max 50 — 70 — µA –50 — –70 — µA — 300 — 500 µA — –300 — –500 µA January 2011 Altera Corporation ...

  • Page 9

    ... Power Consumption You can use the Altera Analyzer to estimate the device power. f For more information about these power analysis tools, refer to the Power Estimator for Altera CPLDs User Guide in volume 3 of the Quartus II Handbook. January 2011 Altera Corporation Device Min 5M40Z — ...

  • Page 10

    ... Timing Model and Specifications MAX V devices timing can be analyzed with the Altera Quartus of industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure MAX V devices have predictable internal delays that allow you to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation ...

  • Page 11

    ... This design is configured for read-only operation in Extended mode. Read and write ability increases the number of logic elements (LEs) used. (3) This design is configured for read-only operation. Read and write ability increases the number of LEs used. (4) This design is asynchronous. 2 (5) The I C megafunction is verified in hardware up to 100-kHz serial clock line rate. January 2011 Altera Corporation Preliminary ...

  • Page 12

    ... Table 3–18 timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and MultiTrack interconnects. f For more information about each internal timing microparameters symbol, refer to AN629: Understanding Timing in Altera Table 3–18. LE Internal Timing Microparameters for MAX V Devices Symbol Parameter LE combinational look-up t ...

  • Page 13

    ... LVCMOS 2 mA — 1.2-V LVCMOS 3 mA — 3.3-V PCI 20 mA — LVDS — — RSDS — — January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Min Max Min Max — 1,319 — 1,543 — 1,045 — 1,276 — ...

  • Page 14

    ... January 2011 Altera Corporation ...

  • Page 15

    ... Address register data in t setup to address register ADS clock Address register data in t hold from address ADH register clock t Data register clock period DCLK January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min Max Min 171 — 174 — ...

  • Page 16

    ... January 2011 Altera Corporation µ ...

  • Page 17

    ... UFM block timing parameters listed in Figure 3–3. UFM Read Waveform ARShft t t ASU ARClk ARDin t DRShft ADS DRClk DRDin DRDout OSC_ENA Program Erase Busy January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Min Max Min Max — 65 — 65 250 — 250 — 250 — ...

  • Page 18

    ... Timing Model and Specifications t DSH t t OSCH OSCS PPMX t OSCH EPMX 5M1270Z/ 5M2210Z Unit C4 C5, I5 Max Min Max 561 — 690 ps 445 — 548 ps 731 — 899 ps January 2011 Altera Corporation ...

  • Page 19

    ... LVTTL or for different drive strengths, use the I/O standard input and output delay adders in f For more information about each external timing parameters symbol, refer to AN629: Understanding Timing in Altera Table 3–26 lists the external I/O timing parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices. ...

  • Page 20

    ... Min 10 pF — 8.1 — — 4.8 — — 1.5 — 1.9 — 0 — 2.0 5.9 2.0 — 216 — 266 January 2011 Altera Corporation C5, I5 Unit Max — ps — ns 118.3 MHz C5, I5 Unit Max 17.7 ns 8.5 ns — ns — ns 8.7 ns — ps — ...

  • Page 21

    ... Parameter t Worst case pin-to-pin delay through one LUT PD1 t Best case pin-to-pin delay through one LUT PD2 t Global clock setup time SU t Global clock hold time H January 2011 Altera Corporation (Note 1), (2) (Part Condition Min Max Min — 216 — 266 — ...

  • Page 22

    ... C4 C5, I5 Min Max Min Max — 0 — 0 — 480 — 591 — 0 — 0 — 480 — 591 — 246 — 303 — 787 — 968 — 695 — 855 — 1,334 — 1,642 January 2011 Altera Corporation Unit ...

  • Page 23

    ... LVCMOS Trigger Without Schmitt 3.3-V PCI Trigger Table 3–34. External Timing Output Delay and t I/O Standard Min 16 mA — 3.3-V LVTTL 8 mA — January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min Max — 1,055 — 1,010 — ...

  • Page 24

    ... Max 6,612 — 6,293 ps 7,313 — 6,994 ps 6,612 — 6,293 ps 7,313 — 6,994 ps 10,021 — 9,702 ps 10,881 — 10,562 ps 21,134 — 20,815 ps 22,399 — 22,080 ps 34,499 — 34,180 ps 36,281 — 35,962 ps 55,796 — 55,477 ps 339 — 418 ps January 2011 Altera Corporation ...

  • Page 25

    ... LVTTL 1.8-V LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS 3.3-V PCI Table 3–38. Maximum Output Clock Rate for I/Os for MAX V Devices (Part 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min Max Min 1,858 — ...

  • Page 26

    ... MHz 120 MHz 304 MHz 304 MHz 200 MHz 5M2210Z Unit C4, C5, I5 Max 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 304 Mbps 55 % 0.2 UI 450 ps 450 ps January 2011 Altera Corporation ...

  • Page 27

    ... RISE t FALL Notes to Table 3–40: (1) For the input clock pin to achieve 200 Mbps, use I/O standard with V (2) This specification is based on external clean clock source. January 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z/5M1270Z/ Mode Min 10 — 9 — 8 — ...

  • Page 28

    ... V CCIO1 = 2.5 V CCIO1 = 1.8 V CCIO1 = 1.5 V CCIO1 (2) (2) (2) (2) Timing Model and Specifications t JPXZ Min Max Unit 55.5 — ns 62.5 — ns 100 — ns 143 — — — — — ns — — — — — ns — — January 2011 Altera Corporation ...

  • Page 29

    ... Document Revision History Table 3–42 lists the revision history for this chapter. Table 3–42. Document Revision History Date Version January 2011 1.1 December 2010 1.0 January 2011 Altera Corporation Parameter , t , and t are maximum values at 35 ns. JPCO JPZX JPXZ Changes Updated Table 3– ...

  • Page 30

    ... MAX V Device Handbook Chapter 3: DC and Switching Characteristics for MAX V Devices Document Revision History January 2011 Altera Corporation ...